| 1# Copyright (c) 2011-2015 Advanced Micro Devices, Inc.
2# All rights reserved.
|
1#
| 3#
|
2# Copyright (c) 2011-2015 Advanced Micro Devices, Inc.
3# All rights reserved.
| 4# For use for simulation and test purposes only
|
4#
| 5#
|
5# For use for simulation and test purposes only
| 6# Redistribution and use in source and binary forms, with or without
7# modification, are permitted provided that the following conditions are met:
|
6#
| 8#
|
7# Redistribution and use in source and binary forms, with or without
8# modification, are permitted provided that the following conditions are met:
| 9# 1. Redistributions of source code must retain the above copyright notice,
10# this list of conditions and the following disclaimer.
|
9#
| 11#
|
10# 1. Redistributions of source code must retain the above copyright notice,
11# this list of conditions and the following disclaimer.
| 12# 2. Redistributions in binary form must reproduce the above copyright notice,
13# this list of conditions and the following disclaimer in the documentation
14# and/or other materials provided with the distribution.
|
12#
| 15#
|
13# 2. Redistributions in binary form must reproduce the above copyright notice,
14# this list of conditions and the following disclaimer in the documentation
15# and/or other materials provided with the distribution.
| 16# 3. Neither the name of the copyright holder nor the names of its
17# contributors may be used to endorse or promote products derived from this
18# software without specific prior written permission.
|
16#
| 19#
|
17# 3. Neither the name of the copyright holder nor the names of its contributors
18# may be used to endorse or promote products derived from this software
19# without specific prior written permission.
| 20# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
24# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30# POSSIBILITY OF SUCH DAMAGE.
|
20#
| 31#
|
21# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
25# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31# POSSIBILITY OF SUCH DAMAGE.
32#
33# Author: Lisa Hsu
34#
| 32# Authors: Lisa Hsu
|
35
36from m5.defines import buildEnv
37from m5.params import *
38from m5.proxy import *
39
40from m5.objects.MemObject import MemObject
41
42if buildEnv['FULL_SYSTEM']:
43 class X86PagetableWalker(MemObject):
44 type = 'X86PagetableWalker'
45 cxx_class = 'X86ISA::Walker'
46 port = SlavePort("Port for the hardware table walker")
47 system = Param.System(Parent.any, "system object")
48
49class X86GPUTLB(MemObject):
50 type = 'X86GPUTLB'
51 cxx_class = 'X86ISA::GpuTLB'
52 cxx_header = 'gpu-compute/gpu_tlb.hh'
53 size = Param.Int(64, "TLB size (number of entries)")
54 assoc = Param.Int(64, "TLB associativity")
55
56 if buildEnv['FULL_SYSTEM']:
57 walker = Param.X86PagetableWalker(X86PagetableWalker(),
58 "page table walker")
59
60 hitLatency = Param.Int(2, "Latency of a TLB hit")
61 missLatency1 = Param.Int(5, "Latency #1 of a TLB miss")
62 missLatency2 = Param.Int(100, "Latency #2 of a TLB miss")
63 maxOutstandingReqs = Param.Int(64, "# of maximum outstanding requests")
64 slave = VectorSlavePort("Port on side closer to CPU/CU")
65 master = VectorMasterPort("Port on side closer to memory")
66 allocationPolicy = Param.Bool(True, "Allocate on an access")
67 accessDistance = Param.Bool(False, "print accessDistance stats")
68
69class TLBCoalescer(MemObject):
70 type = 'TLBCoalescer'
71 cxx_class = 'TLBCoalescer'
72 cxx_header = 'gpu-compute/tlb_coalescer.hh'
73 probesPerCycle = Param.Int(2, "Number of TLB probes per cycle")
74 coalescingWindow = Param.Int(1, "Permit coalescing across that many ticks")
75 slave = VectorSlavePort("Port on side closer to CPU/CU")
76 master = VectorMasterPort("Port on side closer to memory")
77 disableCoalescing = Param.Bool(False,"Dispable Coalescing")
| 33
34from m5.defines import buildEnv
35from m5.params import *
36from m5.proxy import *
37
38from m5.objects.MemObject import MemObject
39
40if buildEnv['FULL_SYSTEM']:
41 class X86PagetableWalker(MemObject):
42 type = 'X86PagetableWalker'
43 cxx_class = 'X86ISA::Walker'
44 port = SlavePort("Port for the hardware table walker")
45 system = Param.System(Parent.any, "system object")
46
47class X86GPUTLB(MemObject):
48 type = 'X86GPUTLB'
49 cxx_class = 'X86ISA::GpuTLB'
50 cxx_header = 'gpu-compute/gpu_tlb.hh'
51 size = Param.Int(64, "TLB size (number of entries)")
52 assoc = Param.Int(64, "TLB associativity")
53
54 if buildEnv['FULL_SYSTEM']:
55 walker = Param.X86PagetableWalker(X86PagetableWalker(),
56 "page table walker")
57
58 hitLatency = Param.Int(2, "Latency of a TLB hit")
59 missLatency1 = Param.Int(5, "Latency #1 of a TLB miss")
60 missLatency2 = Param.Int(100, "Latency #2 of a TLB miss")
61 maxOutstandingReqs = Param.Int(64, "# of maximum outstanding requests")
62 slave = VectorSlavePort("Port on side closer to CPU/CU")
63 master = VectorMasterPort("Port on side closer to memory")
64 allocationPolicy = Param.Bool(True, "Allocate on an access")
65 accessDistance = Param.Bool(False, "print accessDistance stats")
66
67class TLBCoalescer(MemObject):
68 type = 'TLBCoalescer'
69 cxx_class = 'TLBCoalescer'
70 cxx_header = 'gpu-compute/tlb_coalescer.hh'
71 probesPerCycle = Param.Int(2, "Number of TLB probes per cycle")
72 coalescingWindow = Param.Int(1, "Permit coalescing across that many ticks")
73 slave = VectorSlavePort("Port on side closer to CPU/CU")
74 master = VectorMasterPort("Port on side closer to memory")
75 disableCoalescing = Param.Bool(False,"Dispable Coalescing")
|