1#
2# Copyright (c) 2011-2015 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# For use for simulation and test purposes only
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11# this list of conditions and the following disclaimer.
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21# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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32#
33# Author: Lisa Hsu
34#
35
36from m5.defines import buildEnv
37from m5.params import *
38from m5.proxy import *
39
40from m5.objects.MemObject import MemObject
41
42if buildEnv['FULL_SYSTEM']:
43 class X86PagetableWalker(MemObject):
44 type = 'X86PagetableWalker'
45 cxx_class = 'X86ISA::Walker'
46 port = SlavePort("Port for the hardware table walker")
47 system = Param.System(Parent.any, "system object")
48
49class X86GPUTLB(MemObject):
50 type = 'X86GPUTLB'
51 cxx_class = 'X86ISA::GpuTLB'
52 cxx_header = 'gpu-compute/gpu_tlb.hh'
53 size = Param.Int(64, "TLB size (number of entries)")
54 assoc = Param.Int(64, "TLB associativity")
55
56 if buildEnv['FULL_SYSTEM']:
57 walker = Param.X86PagetableWalker(X86PagetableWalker(),
58 "page table walker")
59
60 hitLatency = Param.Int(2, "Latency of a TLB hit")
61 missLatency1 = Param.Int(5, "Latency #1 of a TLB miss")
62 missLatency2 = Param.Int(100, "Latency #2 of a TLB miss")
63 maxOutstandingReqs = Param.Int(64, "# of maximum outstanding requests")
64 slave = VectorSlavePort("Port on side closer to CPU/CU")
65 master = VectorMasterPort("Port on side closer to memory")
66 allocationPolicy = Param.Bool(True, "Allocate on an access")
67 accessDistance = Param.Bool(False, "print accessDistance stats")
68
69class TLBCoalescer(MemObject):
70 type = 'TLBCoalescer'
71 cxx_class = 'TLBCoalescer'
72 cxx_header = 'gpu-compute/tlb_coalescer.hh'
73 probesPerCycle = Param.Int(2, "Number of TLB probes per cycle")
74 coalescingWindow = Param.Int(1, "Permit coalescing across that many ticks")
75 slave = VectorSlavePort("Port on side closer to CPU/CU")
76 master = VectorMasterPort("Port on side closer to memory")
77 disableCoalescing = Param.Bool(False,"Dispable Coalescing")