1#
2# Copyright (c) 2015 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# For use for simulation and test purposes only
6#
7# Redistribution and use in source and binary forms, with or without
8# modification, are permitted provided that the following conditions are met:

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35
36from m5.defines import buildEnv
37from m5.params import *
38from m5.proxy import *
39from m5.SimObject import SimObject
40
41from m5.objects.ClockedObject import ClockedObject
42from m5.objects.Device import DmaDevice
43from m5.objects.Process import EmulatedDriver
44from m5.objects.Bridge import Bridge
45from m5.objects.LdsState import LdsState
46
47class PrefetchType(Enum): vals = [
48 'PF_CU',
49 'PF_PHASE',
50 'PF_WF',

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66 type = 'Wavefront'
67 cxx_class = 'Wavefront'
68 cxx_header = 'gpu-compute/wavefront.hh'
69
70 simdId = Param.Int('SIMD id (0-ComputeUnit.num_SIMDs)')
71 wf_slot_id = Param.Int('wavefront id (0-ComputeUnit.max_wfs)')
72 wfSize = Param.Int(64, 'Wavefront size (in work items)')
73
74class ComputeUnit(ClockedObject):
75 type = 'ComputeUnit'
76 cxx_class = 'ComputeUnit'
77 cxx_header = 'gpu-compute/compute_unit.hh'
78
79 wavefronts = VectorParam.Wavefront('Number of wavefronts')
80 wfSize = Param.Int(64, 'Wavefront size (in work items)')
81 num_SIMDs = Param.Int(4, 'number of SIMD units per CU')
82

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