memory_system.doxygen (9264:1607119c36bb) memory_system.doxygen (13892:0182a0601f66)
1# Copyright (c) 2012 ARM Limited
2# All rights reserved
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license

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46 \section gem5_MS_MH MODEL HIERARCHY
47
48 Model that is used in this document consists of two out-of-order (O3)
49 ARM v7 CPUs with corresponding L1 data caches and Simple Memory. It is
50 created by running gem5 with the following parameters:
51
52 configs/example/fs.py --caches --cpu-type=arm_detailed --num-cpus=2
53
1# Copyright (c) 2012 ARM Limited
2# All rights reserved
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license

--- 37 unchanged lines hidden (view full) ---

46 \section gem5_MS_MH MODEL HIERARCHY
47
48 Model that is used in this document consists of two out-of-order (O3)
49 ARM v7 CPUs with corresponding L1 data caches and Simple Memory. It is
50 created by running gem5 with the following parameters:
51
52 configs/example/fs.py --caches --cpu-type=arm_detailed --num-cpus=2
53
54 Gem5 uses Memory Objects (MemObject) derived objects as basic blocks for
54 Gem5 uses Simulation Objects (SimObject) derived objects as basic blocks for
55 building memory system. They are connected via ports with established
56 master/slave hierarchy. Data flow is initiated on master port while the
57 response messages and snoop queries appear on the slave port. The following
55 building memory system. They are connected via ports with established
56 master/slave hierarchy. Data flow is initiated on master port while the
57 response messages and snoop queries appear on the slave port. The following
58 figure shows the hierarchy of Memory Objects used in this document:
58 figure shows the hierarchy of Simulation Objects used in this document:
59
59
60 \image html "gem5_MS_Fig1.PNG" "Memory Object hierarchy of the model" width=3cm
60 \image html "gem5_MS_Fig1.PNG" "Simulation Object hierarchy of the model" width=3cm
61
62 \section gem5_CPU CPU
63
64 It is not in the scope of this document to describe O3 CPU model in details, so
65 here are only a few relevant notes about the model:
66
67 <b>Read access </b>is initiated by sending message to the port towards DCache
68 object. If DCache rejects the message (for being blocked or busy) CPU will
69 flush the pipeline and the access will be re-attempted later on. The access
70 is completed upon receiving reply message (ReadRep) from DCache.
71
72 <b>Write access</b> is initiated by storing the request into store buffer whose
73 context is emptied and sent to DCache on every tick. DCache may also reject
74 the request. Write access is completed when write reply (WriteRep) message is
75 received from DCache.
76
77 Load & store buffers (for read and write access) don’t impose any
78 restriction on the number of active memory accesses. Therefore, the maximum
79 number of outstanding CPU’s memory access requests is not limited by CPU
61
62 \section gem5_CPU CPU
63
64 It is not in the scope of this document to describe O3 CPU model in details, so
65 here are only a few relevant notes about the model:
66
67 <b>Read access </b>is initiated by sending message to the port towards DCache
68 object. If DCache rejects the message (for being blocked or busy) CPU will
69 flush the pipeline and the access will be re-attempted later on. The access
70 is completed upon receiving reply message (ReadRep) from DCache.
71
72 <b>Write access</b> is initiated by storing the request into store buffer whose
73 context is emptied and sent to DCache on every tick. DCache may also reject
74 the request. Write access is completed when write reply (WriteRep) message is
75 received from DCache.
76
77 Load & store buffers (for read and write access) don’t impose any
78 restriction on the number of active memory accesses. Therefore, the maximum
79 number of outstanding CPU’s memory access requests is not limited by CPU
80 Memory Object but by underlying memory system model.
80 Simulation Object but by underlying memory system model.
81
82 <b>Split memory access</b> is implemented.
83
84 The message that is sent by CPU contains memory type (Normal, Device, Strongly
85 Ordered and cachebility) of the accessed region. However, this is not being used
86 by the rest of the model that takes more simplified approach towards memory types.
87
88 \section gem5_DCache DATA CACHE OBJECT
89
90 Data Cache object implements a standard cache structure:
91
81
82 <b>Split memory access</b> is implemented.
83
84 The message that is sent by CPU contains memory type (Normal, Device, Strongly
85 Ordered and cachebility) of the accessed region. However, this is not being used
86 by the rest of the model that takes more simplified approach towards memory types.
87
88 \section gem5_DCache DATA CACHE OBJECT
89
90 Data Cache object implements a standard cache structure:
91
92 \image html "gem5_MS_Fig2.PNG" "DCache Memory Object" width=3cm
92 \image html "gem5_MS_Fig2.PNG" "DCache Simulation Object" width=3cm
93
94 <b>Cached memory reads</b> that match particular cache tag (with Valid & Read
95 flags) will be completed (by sending ReadResp to CPU) after a configurable time.
96 Otherwise, the request is forwarded to Miss Status and Handling Register
97 (MSHR) block.
98
99 <b>Cached memory writes</b> that match particular cache tag (with Valid, Read
100 & Write flags) will be completed (by sending WriteResp CPU) after the same

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94 <b>Cached memory reads</b> that match particular cache tag (with Valid & Read
95 flags) will be completed (by sending ReadResp to CPU) after a configurable time.
96 Otherwise, the request is forwarded to Miss Status and Handling Register
97 (MSHR) block.
98
99 <b>Cached memory writes</b> that match particular cache tag (with Valid, Read
100 & Write flags) will be completed (by sending WriteResp CPU) after the same

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