pc.cc (5637:3d2451ebad92) pc.cc (5638:dc073dc6358b)
1/*
2 * Copyright (c) 2008 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 33 unchanged lines hidden (view full) ---

42#include "dev/x86/i8254.hh"
43#include "dev/x86/pc.hh"
44#include "dev/x86/south_bridge.hh"
45#include "sim/system.hh"
46
47using namespace std;
48using namespace TheISA;
49
1/*
2 * Copyright (c) 2008 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 33 unchanged lines hidden (view full) ---

42#include "dev/x86/i8254.hh"
43#include "dev/x86/pc.hh"
44#include "dev/x86/south_bridge.hh"
45#include "sim/system.hh"
46
47using namespace std;
48using namespace TheISA;
49
50PC::PC(const Params *p)
50Pc::Pc(const Params *p)
51 : Platform(p), system(p->system)
52{
53 southBridge = NULL;
54 // set the back pointer from the system to myself
55 system->platform = this;
56}
57
58void
51 : Platform(p), system(p->system)
52{
53 southBridge = NULL;
54 // set the back pointer from the system to myself
55 system->platform = this;
56}
57
58void
59PC::init()
59Pc::init()
60{
61 assert(southBridge);
62 I8254 & timer = *southBridge->pit;
63 //Timer 0, mode 2, no bcd, 16 bit count
64 timer.writeControl(0x34);
65 //Timer 0, latch command
66 timer.writeControl(0x00);
67 //Write a 16 bit count of 0
68 timer.writeCounter(0, 0);
69 timer.writeCounter(0, 0);
70}
71
72Tick
60{
61 assert(southBridge);
62 I8254 & timer = *southBridge->pit;
63 //Timer 0, mode 2, no bcd, 16 bit count
64 timer.writeControl(0x34);
65 //Timer 0, latch command
66 timer.writeControl(0x00);
67 //Write a 16 bit count of 0
68 timer.writeCounter(0, 0);
69 timer.writeCounter(0, 0);
70}
71
72Tick
73PC::intrFrequency()
73Pc::intrFrequency()
74{
75 panic("Need implementation\n");
76 M5_DUMMY_RETURN
77}
78
79void
74{
75 panic("Need implementation\n");
76 M5_DUMMY_RETURN
77}
78
79void
80PC::postConsoleInt()
80Pc::postConsoleInt()
81{
82 warn_once("Don't know what interrupt to post for console.\n");
83 //panic("Need implementation\n");
84}
85
86void
81{
82 warn_once("Don't know what interrupt to post for console.\n");
83 //panic("Need implementation\n");
84}
85
86void
87PC::clearConsoleInt()
87Pc::clearConsoleInt()
88{
89 warn_once("Don't know what interrupt to clear for console.\n");
90 //panic("Need implementation\n");
91}
92
93void
88{
89 warn_once("Don't know what interrupt to clear for console.\n");
90 //panic("Need implementation\n");
91}
92
93void
94PC::postPciInt(int line)
94Pc::postPciInt(int line)
95{
96 panic("Need implementation\n");
97}
98
99void
95{
96 panic("Need implementation\n");
97}
98
99void
100PC::clearPciInt(int line)
100Pc::clearPciInt(int line)
101{
102 panic("Need implementation\n");
103}
104
105Addr
101{
102 panic("Need implementation\n");
103}
104
105Addr
106PC::pciToDma(Addr pciAddr) const
106Pc::pciToDma(Addr pciAddr) const
107{
108 panic("Need implementation\n");
109 M5_DUMMY_RETURN
110}
111
112
113Addr
107{
108 panic("Need implementation\n");
109 M5_DUMMY_RETURN
110}
111
112
113Addr
114PC::calcConfigAddr(int bus, int dev, int func)
114Pc::calcConfigAddr(int bus, int dev, int func)
115{
116 assert(func < 8);
117 assert(dev < 32);
118 assert(bus == 0);
119 return (PhysAddrPrefixPciConfig | (func << 8) | (dev << 11));
120}
121
115{
116 assert(func < 8);
117 assert(dev < 32);
118 assert(bus == 0);
119 return (PhysAddrPrefixPciConfig | (func << 8) | (dev << 11));
120}
121
122PC *
123PCParams::create()
122Pc *
123PcParams::create()
124{
124{
125 return new PC(this);
125 return new Pc(this);
126}
126}