pc.cc (5635:b65e232e7755) pc.cc (5636:27a9526eea1f)
1/*
2 * Copyright (c) 2008 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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32 * Implementation of PC platform.
33 */
34
35#include <deque>
36#include <string>
37#include <vector>
38
39#include "arch/x86/x86_traits.hh"
1/*
2 * Copyright (c) 2008 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 23 unchanged lines hidden (view full) ---

32 * Implementation of PC platform.
33 */
34
35#include <deque>
36#include <string>
37#include <vector>
38
39#include "arch/x86/x86_traits.hh"
40#include "dev/intel_8254_timer.hh"
41#include "cpu/intr_control.hh"
42#include "dev/terminal.hh"
40#include "cpu/intr_control.hh"
41#include "dev/terminal.hh"
42#include "dev/x86/i8254.hh"
43#include "dev/x86/pc.hh"
43#include "dev/x86/pc.hh"
44#include "dev/x86/south_bridge/south_bridge.hh"
44#include "sim/system.hh"
45
46using namespace std;
47using namespace TheISA;
48
49PC::PC(const Params *p)
50 : Platform(p), system(p->system)
51{
52 southBridge = NULL;
53 // set the back pointer from the system to myself
54 system->platform = this;
55}
56
57void
58PC::init()
59{
60 assert(southBridge);
45#include "sim/system.hh"
46
47using namespace std;
48using namespace TheISA;
49
50PC::PC(const Params *p)
51 : Platform(p), system(p->system)
52{
53 southBridge = NULL;
54 // set the back pointer from the system to myself
55 system->platform = this;
56}
57
58void
59PC::init()
60{
61 assert(southBridge);
61 Intel8254Timer & timer = southBridge->pit.pit;
62 I8254 & timer = *southBridge->pit;
62 //Timer 0, mode 2, no bcd, 16 bit count
63 timer.writeControl(0x34);
64 //Timer 0, latch command
65 timer.writeControl(0x00);
66 //Write a 16 bit count of 0
67 timer.writeCounter(0, 0);
68 timer.writeCounter(0, 0);
69}

--- 56 unchanged lines hidden --- 		63 //Timer 0, mode 2, no bcd, 16 bit count
64 timer.writeControl(0x34);
65 //Timer 0, latch command
66 timer.writeControl(0x00);
67 //Write a 16 bit count of 0
68 timer.writeCounter(0, 0);
69 timer.writeCounter(0, 0);
70}

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