1/* 2 * Copyright (c) 2008 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 25 unchanged lines hidden (view full) --- 34 35#include <deque> 36#include <string> 37#include <vector> 38 39#include "arch/x86/x86_traits.hh" 40#include "cpu/intr_control.hh" 41#include "dev/terminal.hh" |
42#include "dev/x86/i82094aa.hh" |
43#include "dev/x86/i8254.hh" 44#include "dev/x86/pc.hh" 45#include "dev/x86/south_bridge.hh" 46#include "sim/system.hh" 47 48using namespace std; 49using namespace TheISA; 50 --- 4 unchanged lines hidden (view full) --- 55 // set the back pointer from the system to myself 56 system->platform = this; 57} 58 59void 60Pc::init() 61{ 62 assert(southBridge); |
63 64 /* 65 * Initialize the timer. 66 */ |
67 I8254 & timer = *southBridge->pit; 68 //Timer 0, mode 2, no bcd, 16 bit count 69 timer.writeControl(0x34); 70 //Timer 0, latch command 71 timer.writeControl(0x00); 72 //Write a 16 bit count of 0 73 timer.writeCounter(0, 0); 74 timer.writeCounter(0, 0); |
75 76 /* 77 * Initialize the I/O APIC. 78 */ 79 I82094AA & ioApic = *southBridge->ioApic; 80 I82094AA::RedirTableEntry entry = 0; 81 entry.deliveryMode = 0x7; 82 entry.vector = 0x20; 83 ioApic.writeReg(0x10, entry.bottomDW); 84 ioApic.writeReg(0x11, entry.topDW); |
85} 86 87Tick 88Pc::intrFrequency() 89{ 90 panic("Need implementation\n"); 91 M5_DUMMY_RETURN 92} --- 49 unchanged lines hidden --- |