1/*
2 * Copyright (c) 2008 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 */
30
31/** @file
32 * Implementation of PC platform.
33 */
34
35#include <deque>
36#include <string>
37#include <vector>
38
39#include "arch/x86/intmessage.hh"
40#include "arch/x86/x86_traits.hh"
41#include "config/the_isa.hh"
42#include "cpu/intr_control.hh"
| 1/*
2 * Copyright (c) 2008 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 */
30
31/** @file
32 * Implementation of PC platform.
33 */
34
35#include <deque>
36#include <string>
37#include <vector>
38
39#include "arch/x86/intmessage.hh"
40#include "arch/x86/x86_traits.hh"
41#include "config/the_isa.hh"
42#include "cpu/intr_control.hh"
|
49#include "sim/system.hh"
50
51using namespace std;
52using namespace TheISA;
53
54Pc::Pc(const Params *p)
55 : Platform(p), system(p->system)
56{
57 southBridge = NULL;
58 // set the back pointer from the system to myself
59 system->platform = this;
60}
61
62void
63Pc::init()
64{
65 assert(southBridge);
66
67 /*
68 * Initialize the timer.
69 */
70 I8254 & timer = *southBridge->pit;
71 //Timer 0, mode 2, no bcd, 16 bit count
72 timer.writeControl(0x34);
73 //Timer 0, latch command
74 timer.writeControl(0x00);
75 //Write a 16 bit count of 0
76 timer.writeCounter(0, 0);
77 timer.writeCounter(0, 0);
78
79 /*
80 * Initialize the I/O APIC.
81 */
82 I82094AA & ioApic = *southBridge->ioApic;
83 I82094AA::RedirTableEntry entry = 0;
84 entry.deliveryMode = DeliveryMode::ExtInt;
85 entry.vector = 0x20;
86 ioApic.writeReg(0x10, entry.bottomDW);
87 ioApic.writeReg(0x11, entry.topDW);
88 entry.deliveryMode = DeliveryMode::Fixed;
89 entry.vector = 0x24;
90 ioApic.writeReg(0x18, entry.bottomDW);
91 ioApic.writeReg(0x19, entry.topDW);
92 entry.mask = 1;
93 entry.vector = 0x21;
94 ioApic.writeReg(0x12, entry.bottomDW);
95 ioApic.writeReg(0x13, entry.topDW);
96 entry.vector = 0x20;
97 ioApic.writeReg(0x14, entry.bottomDW);
98 ioApic.writeReg(0x15, entry.topDW);
99 entry.vector = 0x28;
100 ioApic.writeReg(0x20, entry.bottomDW);
101 ioApic.writeReg(0x21, entry.topDW);
102 entry.vector = 0x2C;
103 ioApic.writeReg(0x28, entry.bottomDW);
104 ioApic.writeReg(0x29, entry.topDW);
105 entry.vector = 0x2E;
106 ioApic.writeReg(0x2C, entry.bottomDW);
107 ioApic.writeReg(0x2D, entry.topDW);
108 entry.vector = 0x30;
109 ioApic.writeReg(0x30, entry.bottomDW);
110 ioApic.writeReg(0x31, entry.topDW);
111
112 /*
113 * Mask the PICs. I'm presuming the BIOS/bootloader would have cleared
114 * these out and masked them before passing control to the OS.
115 */
116 southBridge->pic1->maskAll();
117 southBridge->pic2->maskAll();
118}
119
120Tick
121Pc::intrFrequency()
122{
123 panic("Need implementation for intrFrequency\n");
124 M5_DUMMY_RETURN
125}
126
127void
128Pc::postConsoleInt()
129{
130 southBridge->ioApic->signalInterrupt(4);
131 southBridge->pic1->signalInterrupt(4);
132}
133
134void
135Pc::clearConsoleInt()
136{
137 warn_once("Don't know what interrupt to clear for console.\n");
138 //panic("Need implementation\n");
139}
140
141void
142Pc::postPciInt(int line)
143{
144 southBridge->ioApic->signalInterrupt(line);
145}
146
147void
148Pc::clearPciInt(int line)
149{
150 warn_once("Tried to clear PCI interrupt %d\n", line);
151}
152
153Addr
154Pc::pciToDma(Addr pciAddr) const
155{
156 return pciAddr;
157}
158
159Addr
160Pc::calcPciConfigAddr(int bus, int dev, int func)
161{
162 assert(func < 8);
163 assert(dev < 32);
164 assert(bus == 0);
165 return (PhysAddrPrefixPciConfig | (func << 8) | (dev << 11));
166}
167
168Addr
169Pc::calcPciIOAddr(Addr addr)
170{
171 return PhysAddrPrefixIO + addr;
172}
173
174Addr
175Pc::calcPciMemAddr(Addr addr)
176{
177 return addr;
178}
179
180Pc *
181PcParams::create()
182{
183 return new Pc(this);
184}
| 49#include "sim/system.hh"
50
51using namespace std;
52using namespace TheISA;
53
54Pc::Pc(const Params *p)
55 : Platform(p), system(p->system)
56{
57 southBridge = NULL;
58 // set the back pointer from the system to myself
59 system->platform = this;
60}
61
62void
63Pc::init()
64{
65 assert(southBridge);
66
67 /*
68 * Initialize the timer.
69 */
70 I8254 & timer = *southBridge->pit;
71 //Timer 0, mode 2, no bcd, 16 bit count
72 timer.writeControl(0x34);
73 //Timer 0, latch command
74 timer.writeControl(0x00);
75 //Write a 16 bit count of 0
76 timer.writeCounter(0, 0);
77 timer.writeCounter(0, 0);
78
79 /*
80 * Initialize the I/O APIC.
81 */
82 I82094AA & ioApic = *southBridge->ioApic;
83 I82094AA::RedirTableEntry entry = 0;
84 entry.deliveryMode = DeliveryMode::ExtInt;
85 entry.vector = 0x20;
86 ioApic.writeReg(0x10, entry.bottomDW);
87 ioApic.writeReg(0x11, entry.topDW);
88 entry.deliveryMode = DeliveryMode::Fixed;
89 entry.vector = 0x24;
90 ioApic.writeReg(0x18, entry.bottomDW);
91 ioApic.writeReg(0x19, entry.topDW);
92 entry.mask = 1;
93 entry.vector = 0x21;
94 ioApic.writeReg(0x12, entry.bottomDW);
95 ioApic.writeReg(0x13, entry.topDW);
96 entry.vector = 0x20;
97 ioApic.writeReg(0x14, entry.bottomDW);
98 ioApic.writeReg(0x15, entry.topDW);
99 entry.vector = 0x28;
100 ioApic.writeReg(0x20, entry.bottomDW);
101 ioApic.writeReg(0x21, entry.topDW);
102 entry.vector = 0x2C;
103 ioApic.writeReg(0x28, entry.bottomDW);
104 ioApic.writeReg(0x29, entry.topDW);
105 entry.vector = 0x2E;
106 ioApic.writeReg(0x2C, entry.bottomDW);
107 ioApic.writeReg(0x2D, entry.topDW);
108 entry.vector = 0x30;
109 ioApic.writeReg(0x30, entry.bottomDW);
110 ioApic.writeReg(0x31, entry.topDW);
111
112 /*
113 * Mask the PICs. I'm presuming the BIOS/bootloader would have cleared
114 * these out and masked them before passing control to the OS.
115 */
116 southBridge->pic1->maskAll();
117 southBridge->pic2->maskAll();
118}
119
120Tick
121Pc::intrFrequency()
122{
123 panic("Need implementation for intrFrequency\n");
124 M5_DUMMY_RETURN
125}
126
127void
128Pc::postConsoleInt()
129{
130 southBridge->ioApic->signalInterrupt(4);
131 southBridge->pic1->signalInterrupt(4);
132}
133
134void
135Pc::clearConsoleInt()
136{
137 warn_once("Don't know what interrupt to clear for console.\n");
138 //panic("Need implementation\n");
139}
140
141void
142Pc::postPciInt(int line)
143{
144 southBridge->ioApic->signalInterrupt(line);
145}
146
147void
148Pc::clearPciInt(int line)
149{
150 warn_once("Tried to clear PCI interrupt %d\n", line);
151}
152
153Addr
154Pc::pciToDma(Addr pciAddr) const
155{
156 return pciAddr;
157}
158
159Addr
160Pc::calcPciConfigAddr(int bus, int dev, int func)
161{
162 assert(func < 8);
163 assert(dev < 32);
164 assert(bus == 0);
165 return (PhysAddrPrefixPciConfig | (func << 8) | (dev << 11));
166}
167
168Addr
169Pc::calcPciIOAddr(Addr addr)
170{
171 return PhysAddrPrefixIO + addr;
172}
173
174Addr
175Pc::calcPciMemAddr(Addr addr)
176{
177 return addr;
178}
179
180Pc *
181PcParams::create()
182{
183 return new Pc(this);
184}
|