1/*
2 * Copyright (c) 2008 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 */
30
31/** @file
32 * Implementation of PC platform.
33 */
34
35#include <deque>
36#include <string>
37#include <vector>
38
39#include "arch/x86/x86_traits.hh"
| 1/*
2 * Copyright (c) 2008 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 */
30
31/** @file
32 * Implementation of PC platform.
33 */
34
35#include <deque>
36#include <string>
37#include <vector>
38
39#include "arch/x86/x86_traits.hh"
|
40#include "dev/intel_8254_timer.hh"
| |
41#include "cpu/intr_control.hh"
42#include "dev/terminal.hh"
| 40#include "cpu/intr_control.hh"
41#include "dev/terminal.hh"
|
| 42#include "dev/x86/i8254.hh"
|
43#include "dev/x86/pc.hh"
| 43#include "dev/x86/pc.hh"
|
| 44#include "dev/x86/south_bridge/south_bridge.hh"
|
44#include "sim/system.hh"
45
46using namespace std;
47using namespace TheISA;
48
49PC::PC(const Params *p)
50 : Platform(p), system(p->system)
51{
52 southBridge = NULL;
53 // set the back pointer from the system to myself
54 system->platform = this;
55}
56
57void
58PC::init()
59{
60 assert(southBridge);
| 45#include "sim/system.hh"
46
47using namespace std;
48using namespace TheISA;
49
50PC::PC(const Params *p)
51 : Platform(p), system(p->system)
52{
53 southBridge = NULL;
54 // set the back pointer from the system to myself
55 system->platform = this;
56}
57
58void
59PC::init()
60{
61 assert(southBridge);
|
61 Intel8254Timer & timer = southBridge->pit.pit;
| 62 I8254 & timer = *southBridge->pit;
|
62 //Timer 0, mode 2, no bcd, 16 bit count
63 timer.writeControl(0x34);
64 //Timer 0, latch command
65 timer.writeControl(0x00);
66 //Write a 16 bit count of 0
67 timer.writeCounter(0, 0);
68 timer.writeCounter(0, 0);
69}
70
71Tick
72PC::intrFrequency()
73{
74 panic("Need implementation\n");
75 M5_DUMMY_RETURN
76}
77
78void
79PC::postConsoleInt()
80{
81 warn_once("Don't know what interrupt to post for console.\n");
82 //panic("Need implementation\n");
83}
84
85void
86PC::clearConsoleInt()
87{
88 warn_once("Don't know what interrupt to clear for console.\n");
89 //panic("Need implementation\n");
90}
91
92void
93PC::postPciInt(int line)
94{
95 panic("Need implementation\n");
96}
97
98void
99PC::clearPciInt(int line)
100{
101 panic("Need implementation\n");
102}
103
104Addr
105PC::pciToDma(Addr pciAddr) const
106{
107 panic("Need implementation\n");
108 M5_DUMMY_RETURN
109}
110
111
112Addr
113PC::calcConfigAddr(int bus, int dev, int func)
114{
115 assert(func < 8);
116 assert(dev < 32);
117 assert(bus == 0);
118 return (PhysAddrPrefixPciConfig | (func << 8) | (dev << 11));
119}
120
121PC *
122PCParams::create()
123{
124 return new PC(this);
125}
| 63 //Timer 0, mode 2, no bcd, 16 bit count
64 timer.writeControl(0x34);
65 //Timer 0, latch command
66 timer.writeControl(0x00);
67 //Write a 16 bit count of 0
68 timer.writeCounter(0, 0);
69 timer.writeCounter(0, 0);
70}
71
72Tick
73PC::intrFrequency()
74{
75 panic("Need implementation\n");
76 M5_DUMMY_RETURN
77}
78
79void
80PC::postConsoleInt()
81{
82 warn_once("Don't know what interrupt to post for console.\n");
83 //panic("Need implementation\n");
84}
85
86void
87PC::clearConsoleInt()
88{
89 warn_once("Don't know what interrupt to clear for console.\n");
90 //panic("Need implementation\n");
91}
92
93void
94PC::postPciInt(int line)
95{
96 panic("Need implementation\n");
97}
98
99void
100PC::clearPciInt(int line)
101{
102 panic("Need implementation\n");
103}
104
105Addr
106PC::pciToDma(Addr pciAddr) const
107{
108 panic("Need implementation\n");
109 M5_DUMMY_RETURN
110}
111
112
113Addr
114PC::calcConfigAddr(int bus, int dev, int func)
115{
116 assert(func < 8);
117 assert(dev < 32);
118 assert(bus == 0);
119 return (PhysAddrPrefixPciConfig | (func << 8) | (dev << 11));
120}
121
122PC *
123PCParams::create()
124{
125 return new PC(this);
126}
|