1/*
2 * Copyright (c) 2008 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 */
30
31/** @file
32 * Implementation of PC platform.
33 */
34
35#include <deque>
36#include <string>
37#include <vector>
38
39#include "arch/x86/intmessage.hh"
40#include "arch/x86/x86_traits.hh"
41#include "config/the_isa.hh"
42#include "cpu/intr_control.hh"
43#include "dev/x86/i82094aa.hh"
44#include "dev/x86/i8254.hh"
45#include "dev/x86/i8259.hh"
46#include "dev/x86/pc.hh"
47#include "dev/x86/south_bridge.hh"
48#include "dev/terminal.hh"
49#include "sim/system.hh"
50
51using namespace std;
52using namespace TheISA;
53
54Pc::Pc(const Params *p)
55 : Platform(p), system(p->system)
56{
57 southBridge = NULL;
58 // set the back pointer from the system to myself
59#if FULL_SYSTEM //XXX No platform pointer in SE mode.
60 system->platform = this;
61#endif
62}
63
64void
65Pc::init()
66{
67 assert(southBridge);
68
69 /*
70 * Initialize the timer.
71 */
72 I8254 & timer = *southBridge->pit;
73 //Timer 0, mode 2, no bcd, 16 bit count
74 timer.writeControl(0x34);
75 //Timer 0, latch command
76 timer.writeControl(0x00);
77 //Write a 16 bit count of 0
78 timer.writeCounter(0, 0);
79 timer.writeCounter(0, 0);
80
81 /*
82 * Initialize the I/O APIC.
83 */
84 I82094AA & ioApic = *southBridge->ioApic;
85 I82094AA::RedirTableEntry entry = 0;
86 entry.deliveryMode = DeliveryMode::ExtInt;
87 entry.vector = 0x20;
88 ioApic.writeReg(0x10, entry.bottomDW);
89 ioApic.writeReg(0x11, entry.topDW);
90 entry.deliveryMode = DeliveryMode::Fixed;
91 entry.vector = 0x24;
92 ioApic.writeReg(0x18, entry.bottomDW);
93 ioApic.writeReg(0x19, entry.topDW);
94 entry.mask = 1;
95 entry.vector = 0x21;
96 ioApic.writeReg(0x12, entry.bottomDW);
97 ioApic.writeReg(0x13, entry.topDW);
98 entry.vector = 0x20;
99 ioApic.writeReg(0x14, entry.bottomDW);
100 ioApic.writeReg(0x15, entry.topDW);
101 entry.vector = 0x28;
102 ioApic.writeReg(0x20, entry.bottomDW);
103 ioApic.writeReg(0x21, entry.topDW);
104 entry.vector = 0x2C;
105 ioApic.writeReg(0x28, entry.bottomDW);
106 ioApic.writeReg(0x29, entry.topDW);
107 entry.vector = 0x2E;
108 ioApic.writeReg(0x2C, entry.bottomDW);
109 ioApic.writeReg(0x2D, entry.topDW);
110 entry.vector = 0x30;
111 ioApic.writeReg(0x30, entry.bottomDW);
112 ioApic.writeReg(0x31, entry.topDW);
113
114 /*
115 * Mask the PICs. I'm presuming the BIOS/bootloader would have cleared
116 * these out and masked them before passing control to the OS.
117 */
118 southBridge->pic1->maskAll();
119 southBridge->pic2->maskAll();
120}
121
122Tick
123Pc::intrFrequency()
124{
125 panic("Need implementation for intrFrequency\n");
126 M5_DUMMY_RETURN
127}
128
129void
130Pc::postConsoleInt()
131{
132 southBridge->ioApic->signalInterrupt(4);
133 southBridge->pic1->signalInterrupt(4);
134}
135
136void
137Pc::clearConsoleInt()
138{
139 warn_once("Don't know what interrupt to clear for console.\n");
140 //panic("Need implementation\n");
141}
142
143void
144Pc::postPciInt(int line)
145{
146 southBridge->ioApic->signalInterrupt(line);
147}
148
149void
150Pc::clearPciInt(int line)
151{
152 warn_once("Tried to clear PCI interrupt %d\n", line);
153}
154
155Addr
156Pc::pciToDma(Addr pciAddr) const
157{
158 return pciAddr;
159}
160
161Addr
162Pc::calcPciConfigAddr(int bus, int dev, int func)
163{
164 assert(func < 8);
165 assert(dev < 32);
166 assert(bus == 0);
167 return (PhysAddrPrefixPciConfig | (func << 8) | (dev << 11));
168}
169
170Addr
171Pc::calcPciIOAddr(Addr addr)
172{
173 return PhysAddrPrefixIO + addr;
174}
175
176Addr
177Pc::calcPciMemAddr(Addr addr)
178{
179 return addr;
180}
181
182Pc *
183PcParams::create()
184{
185 return new Pc(this);
186}