1/*
2 * Copyright (c) 2008 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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34
35#include <deque>
36#include <string>
37#include <vector>
38
39#include "arch/x86/x86_traits.hh"
40#include "cpu/intr_control.hh"
41#include "dev/terminal.hh"
42#include "dev/x86/i8254.hh"
43#include "dev/x86/pc.hh"
44#include "dev/x86/south_bridge.hh"
45#include "sim/system.hh"
46
47using namespace std;
48using namespace TheISA;
49

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54 // set the back pointer from the system to myself
55 system->platform = this;
56}
57
58void
59Pc::init()
60{
61 assert(southBridge);
62 I8254 & timer = *southBridge->pit;
63 //Timer 0, mode 2, no bcd, 16 bit count
64 timer.writeControl(0x34);
65 //Timer 0, latch command
66 timer.writeControl(0x00);
67 //Write a 16 bit count of 0
68 timer.writeCounter(0, 0);
69 timer.writeCounter(0, 0);
70}
71
72Tick
73Pc::intrFrequency()
74{
75 panic("Need implementation\n");
76 M5_DUMMY_RETURN
77}

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