intdev.hh (8851:7e966326ef5b) intdev.hh (8922:17f037ad8918)
1/*
1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
2 * Copyright (c) 2008 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright

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46
47namespace X86ISA {
48
49typedef std::list<int> ApicList;
50
51class IntDev
52{
53 protected:
14 * Copyright (c) 2008 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright

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58
59namespace X86ISA {
60
61typedef std::list<int> ApicList;
62
63class IntDev
64{
65 protected:
54 class IntPort : public MessagePort
66 class IntSlavePort : public MessageSlavePort
55 {
56 IntDev * device;
57 Tick latency;
67 {
68 IntDev * device;
69 Tick latency;
58 Addr intAddr;
59 public:
70 public:
60 IntPort(const std::string &_name, MemObject * _parent,
61 IntDev *dev, Tick _latency) :
62 MessagePort(_name, _parent), device(dev), latency(_latency)
71 IntSlavePort(const std::string& _name, MemObject* _parent,
72 IntDev* dev, Tick _latency) :
73 MessageSlavePort(_name, _parent), device(dev), latency(_latency)
63 {
64 }
65
66 AddrRangeList getAddrRanges()
67 {
68 return device->getIntAddrRange();
69 }
70
71 Tick recvMessage(PacketPtr pkt)
72 {
73 return device->recvMessage(pkt);
74 }
74 {
75 }
76
77 AddrRangeList getAddrRanges()
78 {
79 return device->getIntAddrRange();
80 }
81
82 Tick recvMessage(PacketPtr pkt)
83 {
84 return device->recvMessage(pkt);
85 }
86 };
75
87
88 class IntMasterPort : public MessageMasterPort
89 {
90 IntDev* device;
91 Tick latency;
92 public:
93 IntMasterPort(const std::string& _name, MemObject* _parent,
94 IntDev* dev, Tick _latency) :
95 MessageMasterPort(_name, _parent), device(dev), latency(_latency)
96 {
97 }
98
76 Tick recvResponse(PacketPtr pkt)
77 {
78 return device->recvResponse(pkt);
79 }
80
81 // This is x86 focused, so if this class becomes generic, this would
82 // need to be moved into a subclass.
83 void sendMessage(ApicList apics,
84 TriggerIntMessage message, bool timing);
85 };
86
99 Tick recvResponse(PacketPtr pkt)
100 {
101 return device->recvResponse(pkt);
102 }
103
104 // This is x86 focused, so if this class becomes generic, this would
105 // need to be moved into a subclass.
106 void sendMessage(ApicList apics,
107 TriggerIntMessage message, bool timing);
108 };
109
87 IntPort intPort;
110 IntMasterPort intMasterPort;
88
89 public:
90 IntDev(MemObject * parent, Tick latency = 0) :
111
112 public:
113 IntDev(MemObject * parent, Tick latency = 0) :
91 intPort(parent->name() + ".int_master", parent, this, latency)
114 intMasterPort(parent->name() + ".int_master", parent, this, latency)
92 {
93 }
94
95 virtual ~IntDev()
96 {}
97
98 virtual void init();
99

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116 }
117
118 virtual ~IntDev()
119 {}
120
121 virtual void init();
122

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