1/* 2 * Copyright (c) 2008 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 29 unchanged lines hidden (view full) --- 38#include "arch/x86/intmessage.hh" 39#include "mem/mem_object.hh" 40#include "mem/mport.hh" 41#include "sim/sim_object.hh" 42#include "params/X86IntSourcePin.hh" 43#include "params/X86IntSinkPin.hh" 44#include "params/X86IntLine.hh" 45 |
46#include <list> 47 |
48namespace X86ISA { 49 |
50typedef std::list<int> ApicList; 51 |
52class IntDev 53{ 54 protected: 55 class IntPort : public MessagePort 56 { 57 IntDev * device; 58 Tick latency; 59 Addr intAddr; --- 17 unchanged lines hidden (view full) --- 77 78 Tick recvResponse(PacketPtr pkt) 79 { 80 return device->recvResponse(pkt); 81 } 82 83 // This is x86 focused, so if this class becomes generic, this would 84 // need to be moved into a subclass. |
85 void sendMessage(ApicList apics, 86 TriggerIntMessage message, bool timing); |
87 88 void recvStatusChange(Status status) 89 { 90 if (status == RangeChange) { 91 sendStatusChange(Port::RangeChange); 92 } 93 } 94 --- 145 unchanged lines hidden --- |