1/* 2 * Copyright (c) 2012 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 35 unchanged lines hidden (view full) --- 44#define __DEV_X86_INTDEV_HH__ 45 46#include <cassert> 47#include <list> 48#include <string> 49 50#include "arch/x86/intmessage.hh" 51#include "arch/x86/x86_traits.hh" |
52#include "mem/tport.hh" |
53#include "sim/sim_object.hh" 54 |
55namespace X86ISA 56{ |
57 58template <class Device> 59class IntSlavePort : public SimpleTimingPort 60{ 61 Device * device; 62 63 public: 64 IntSlavePort(const std::string& _name, SimObject* _parent, --- 16 unchanged lines hidden (view full) --- 81 name(), pkt->cmd.toString(), getPeer()); 82 pkt->headerDelay = pkt->payloadDelay = 0; 83 return device->recvMessage(pkt); 84 } 85}; 86 87typedef std::list<int> ApicList; 88 |
89template <class Device> 90class IntMasterPort : public QueuedMasterPort |
91{ |
92 ReqPacketQueue reqQueue; 93 SnoopRespPacketQueue snoopRespQueue; |
94 |
95 Device* device; 96 Tick latency; 97 98 public: 99 IntMasterPort(const std::string& _name, SimObject* _parent, 100 Device* dev, Tick _latency) : 101 QueuedMasterPort(_name, _parent, reqQueue, snoopRespQueue), 102 reqQueue(*_parent, *this), snoopRespQueue(*_parent, *this), 103 device(dev), latency(_latency) |
104 { |
105 } |
106 |
107 bool 108 recvTimingResp(PacketPtr pkt) override 109 { 110 return device->recvResponse(pkt); 111 } 112 113 // This is x86 focused, so if this class becomes generic, this would 114 // need to be moved into a subclass. 115 void 116 sendMessage(X86ISA::ApicList apics, TriggerIntMessage message, bool timing) 117 { 118 for (auto id: apics) { 119 PacketPtr pkt = buildIntRequest(id, message); 120 if (timing) { 121 schedTimingReq(pkt, curTick() + latency); 122 // The target handles cleaning up the packet in timing mode. 123 } else { 124 // ignore the latency involved in the atomic transaction 125 sendAtomic(pkt); 126 assert(pkt->isResponse()); 127 // also ignore the latency in handling the response 128 device->recvResponse(pkt); 129 } |
130 } |
131 } 132}; |
133 |
134class IntDevice 135{ 136 protected: |
137 |
138 IntMasterPort<IntDevice> intMasterPort; |
139 140 public: 141 IntDevice(SimObject * parent, Tick latency = 0) : 142 intMasterPort(parent->name() + ".int_master", parent, this, latency) 143 { 144 } 145 146 virtual ~IntDevice() 147 {} 148 149 virtual void init(); 150 |
151 virtual bool |
152 recvResponse(PacketPtr pkt) 153 { 154 panic("recvResponse not implemented.\n"); |
155 } 156}; 157 158} // namespace X86ISA 159 160#endif //__DEV_X86_INTDEV_HH__ |