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< #include "mem/mport.hh"
---
> #include "mem/tport.hh"
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< namespace X86ISA {
---
> namespace X86ISA
> {
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< class IntDevice
---
> template <class Device>
> class IntMasterPort : public QueuedMasterPort
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< protected:
---
> ReqPacketQueue reqQueue;
> SnoopRespPacketQueue snoopRespQueue;
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< class IntMasterPort : public MessageMasterPort
---
> Device* device;
> Tick latency;
>
> public:
> IntMasterPort(const std::string& _name, SimObject* _parent,
> Device* dev, Tick _latency) :
> QueuedMasterPort(_name, _parent, reqQueue, snoopRespQueue),
> reqQueue(*_parent, *this), snoopRespQueue(*_parent, *this),
> device(dev), latency(_latency)
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< IntDevice* device;
< Tick latency;
< public:
< IntMasterPort(const std::string& _name, SimObject* _parent,
< IntDevice* dev, Tick _latency) :
< MessageMasterPort(_name, _parent), device(dev), latency(_latency)
< {
< }
---
> }
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< Tick recvResponse(PacketPtr pkt)
< {
< return device->recvResponse(pkt);
---
> bool
> recvTimingResp(PacketPtr pkt) override
> {
> return device->recvResponse(pkt);
> }
>
> // This is x86 focused, so if this class becomes generic, this would
> // need to be moved into a subclass.
> void
> sendMessage(X86ISA::ApicList apics, TriggerIntMessage message, bool timing)
> {
> for (auto id: apics) {
> PacketPtr pkt = buildIntRequest(id, message);
> if (timing) {
> schedTimingReq(pkt, curTick() + latency);
> // The target handles cleaning up the packet in timing mode.
> } else {
> // ignore the latency involved in the atomic transaction
> sendAtomic(pkt);
> assert(pkt->isResponse());
> // also ignore the latency in handling the response
> device->recvResponse(pkt);
> }
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> }
> };
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< // This is x86 focused, so if this class becomes generic, this would
< // need to be moved into a subclass.
< void sendMessage(ApicList apics,
< TriggerIntMessage message, bool timing);
< };
---
> class IntDevice
> {
> protected:
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< IntMasterPort intMasterPort;
---
> IntMasterPort<IntDevice> intMasterPort;
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< virtual Tick
---
> virtual bool
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< return 0;