1/*
2 * Copyright (c) 2008 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 */
30
31#ifndef __DEV_X86_INTDEV_HH__
32#define __DEV_X86_INTDEV_HH__
33
34#include <assert.h>
35#include <string>
36
37#include "arch/x86/x86_traits.hh"
38#include "arch/x86/intmessage.hh"
39#include "mem/mem_object.hh"
40#include "mem/mport.hh"
41#include "sim/sim_object.hh"
42#include "params/X86IntSourcePin.hh"
43#include "params/X86IntSinkPin.hh"
44#include "params/X86IntLine.hh"
45
46namespace X86ISA {
47
48class IntDev
49{
50 protected:
51 class IntPort : public MessagePort
52 {
53 IntDev * device;
54 Tick latency;
55 Addr intAddr;
56 public:
57 IntPort(const std::string &_name, MemObject * _parent,
58 IntDev *dev, Tick _latency) :
59 MessagePort(_name, _parent), device(dev), latency(_latency)
60 {
61 }
62
63 void getDeviceAddressRanges(AddrRangeList &resp, bool &snoop)
64 {
65 snoop = false;
66 device->getIntAddrRange(resp);
67 }
68
69 Tick recvMessage(PacketPtr pkt)
70 {
71 return device->recvMessage(pkt);
72 }
73
| 1/*
2 * Copyright (c) 2008 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 */
30
31#ifndef __DEV_X86_INTDEV_HH__
32#define __DEV_X86_INTDEV_HH__
33
34#include <assert.h>
35#include <string>
36
37#include "arch/x86/x86_traits.hh"
38#include "arch/x86/intmessage.hh"
39#include "mem/mem_object.hh"
40#include "mem/mport.hh"
41#include "sim/sim_object.hh"
42#include "params/X86IntSourcePin.hh"
43#include "params/X86IntSinkPin.hh"
44#include "params/X86IntLine.hh"
45
46namespace X86ISA {
47
48class IntDev
49{
50 protected:
51 class IntPort : public MessagePort
52 {
53 IntDev * device;
54 Tick latency;
55 Addr intAddr;
56 public:
57 IntPort(const std::string &_name, MemObject * _parent,
58 IntDev *dev, Tick _latency) :
59 MessagePort(_name, _parent), device(dev), latency(_latency)
60 {
61 }
62
63 void getDeviceAddressRanges(AddrRangeList &resp, bool &snoop)
64 {
65 snoop = false;
66 device->getIntAddrRange(resp);
67 }
68
69 Tick recvMessage(PacketPtr pkt)
70 {
71 return device->recvMessage(pkt);
72 }
73
|
74 // This is x86 focused, so if this class becomes generic, this would
75 // need to be moved into a subclass.
76 void sendMessage(TriggerIntMessage message, bool timing);
77
78 void recvStatusChange(Status status)
79 {
80 if (status == RangeChange) {
81 sendStatusChange(Port::RangeChange);
82 }
83 }
84
85 };
86
87 IntPort * intPort;
88
89 public:
90 IntDev(MemObject * parent, Tick latency = 0)
91 {
92 if (parent != NULL) {
93 intPort = new IntPort(parent->name() + ".int_port",
94 parent, this, latency);
95 } else {
96 intPort = NULL;
97 }
98 }
99
100 virtual ~IntDev()
101 {}
102
103 virtual void
104 signalInterrupt(int line)
105 {
106 panic("signalInterrupt not implemented.\n");
107 }
108
109 virtual void
110 raiseInterruptPin(int number)
111 {
112 panic("raiseInterruptPin not implemented.\n");
113 }
114
115 virtual void
116 lowerInterruptPin(int number)
117 {
118 panic("lowerInterruptPin not implemented.\n");
119 }
120
121 virtual Tick
122 recvMessage(PacketPtr pkt)
123 {
124 panic("recvMessage not implemented.\n");
125 return 0;
126 }
127
| 79 // This is x86 focused, so if this class becomes generic, this would
80 // need to be moved into a subclass.
81 void sendMessage(TriggerIntMessage message, bool timing);
82
83 void recvStatusChange(Status status)
84 {
85 if (status == RangeChange) {
86 sendStatusChange(Port::RangeChange);
87 }
88 }
89
90 };
91
92 IntPort * intPort;
93
94 public:
95 IntDev(MemObject * parent, Tick latency = 0)
96 {
97 if (parent != NULL) {
98 intPort = new IntPort(parent->name() + ".int_port",
99 parent, this, latency);
100 } else {
101 intPort = NULL;
102 }
103 }
104
105 virtual ~IntDev()
106 {}
107
108 virtual void
109 signalInterrupt(int line)
110 {
111 panic("signalInterrupt not implemented.\n");
112 }
113
114 virtual void
115 raiseInterruptPin(int number)
116 {
117 panic("raiseInterruptPin not implemented.\n");
118 }
119
120 virtual void
121 lowerInterruptPin(int number)
122 {
123 panic("lowerInterruptPin not implemented.\n");
124 }
125
126 virtual Tick
127 recvMessage(PacketPtr pkt)
128 {
129 panic("recvMessage not implemented.\n");
130 return 0;
131 }
132
|
128 virtual void
129 getIntAddrRange(AddrRangeList &range_list)
130 {
131 panic("intAddrRange not implemented.\n");
132 }
133};
134
135class IntSinkPin : public SimObject
136{
137 public:
138 IntDev * device;
139 int number;
140
141 typedef X86IntSinkPinParams Params;
142
143 const Params *
144 params() const
145 {
146 return dynamic_cast<const Params *>(_params);
147 }
148
149 IntSinkPin(Params *p) : SimObject(p),
150 device(dynamic_cast<IntDev *>(p->device)), number(p->number)
151 {
152 assert(device);
153 }
154};
155
156class IntSourcePin : public SimObject
157{
158 protected:
159 std::vector<IntSinkPin *> sinks;
160
161 public:
162 typedef X86IntSourcePinParams Params;
163
164 const Params *
165 params() const
166 {
167 return dynamic_cast<const Params *>(_params);
168 }
169
170 void
171 addSink(IntSinkPin *sink)
172 {
173 sinks.push_back(sink);
174 }
175
176 void
177 raise()
178 {
179 for (int i = 0; i < sinks.size(); i++) {
180 const IntSinkPin &pin = *sinks[i];
181 pin.device->raiseInterruptPin(pin.number);
182 }
183 }
184
185 void
186 lower()
187 {
188 for (int i = 0; i < sinks.size(); i++) {
189 const IntSinkPin &pin = *sinks[i];
190 pin.device->lowerInterruptPin(pin.number);
191 }
192 }
193
194 IntSourcePin(Params *p) : SimObject(p)
195 {}
196};
197
198class IntLine : public SimObject
199{
200 protected:
201 IntSourcePin *source;
202 IntSinkPin *sink;
203
204 public:
205 typedef X86IntLineParams Params;
206
207 const Params *
208 params() const
209 {
210 return dynamic_cast<const Params *>(_params);
211 }
212
213 IntLine(Params *p) : SimObject(p), source(p->source), sink(p->sink)
214 {
215 source->addSink(sink);
216 }
217};
218
219}; // namespace X86ISA
220
221#endif //__DEV_X86_INTDEV_HH__
| 141 virtual void
142 getIntAddrRange(AddrRangeList &range_list)
143 {
144 panic("intAddrRange not implemented.\n");
145 }
146};
147
148class IntSinkPin : public SimObject
149{
150 public:
151 IntDev * device;
152 int number;
153
154 typedef X86IntSinkPinParams Params;
155
156 const Params *
157 params() const
158 {
159 return dynamic_cast<const Params *>(_params);
160 }
161
162 IntSinkPin(Params *p) : SimObject(p),
163 device(dynamic_cast<IntDev *>(p->device)), number(p->number)
164 {
165 assert(device);
166 }
167};
168
169class IntSourcePin : public SimObject
170{
171 protected:
172 std::vector<IntSinkPin *> sinks;
173
174 public:
175 typedef X86IntSourcePinParams Params;
176
177 const Params *
178 params() const
179 {
180 return dynamic_cast<const Params *>(_params);
181 }
182
183 void
184 addSink(IntSinkPin *sink)
185 {
186 sinks.push_back(sink);
187 }
188
189 void
190 raise()
191 {
192 for (int i = 0; i < sinks.size(); i++) {
193 const IntSinkPin &pin = *sinks[i];
194 pin.device->raiseInterruptPin(pin.number);
195 }
196 }
197
198 void
199 lower()
200 {
201 for (int i = 0; i < sinks.size(); i++) {
202 const IntSinkPin &pin = *sinks[i];
203 pin.device->lowerInterruptPin(pin.number);
204 }
205 }
206
207 IntSourcePin(Params *p) : SimObject(p)
208 {}
209};
210
211class IntLine : public SimObject
212{
213 protected:
214 IntSourcePin *source;
215 IntSinkPin *sink;
216
217 public:
218 typedef X86IntLineParams Params;
219
220 const Params *
221 params() const
222 {
223 return dynamic_cast<const Params *>(_params);
224 }
225
226 IntLine(Params *p) : SimObject(p), source(p->source), sink(p->sink)
227 {
228 source->addSink(sink);
229 }
230};
231
232}; // namespace X86ISA
233
234#endif //__DEV_X86_INTDEV_HH__
|