1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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44#define __DEV_X86_INTDEV_HH__
45
46#include <cassert>
47#include <list>
48#include <string>
49
50#include "arch/x86/intmessage.hh"
51#include "arch/x86/x86_traits.hh"
52#include "mem/mport.hh"
53#include "sim/sim_object.hh"
54
55namespace X86ISA {
56
57template <class Device>
58class IntSlavePort : public SimpleTimingPort
59{
60 Device * device;
61
62 public:
63 IntSlavePort(const std::string& _name, SimObject* _parent,

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80 name(), pkt->cmd.toString(), getPeer());
81 pkt->headerDelay = pkt->payloadDelay = 0;
82 return device->recvMessage(pkt);
83 }
84};
85
86typedef std::list<int> ApicList;
87
88class IntDevice
89{
90 protected:
91
92 class IntMasterPort : public MessageMasterPort
93 {
94 IntDevice* device;
95 Tick latency;
96 public:
97 IntMasterPort(const std::string& _name, SimObject* _parent,
98 IntDevice* dev, Tick _latency) :
99 MessageMasterPort(_name, _parent), device(dev), latency(_latency)
100 {
101 }
102
103 Tick recvResponse(PacketPtr pkt)
104 {
105 return device->recvResponse(pkt);
106 }
107
108 // This is x86 focused, so if this class becomes generic, this would
109 // need to be moved into a subclass.
110 void sendMessage(ApicList apics,
111 TriggerIntMessage message, bool timing);
112 };
113
114 IntMasterPort intMasterPort;
115
116 public:
117 IntDevice(SimObject * parent, Tick latency = 0) :
118 intMasterPort(parent->name() + ".int_master", parent, this, latency)
119 {
120 }
121
122 virtual ~IntDevice()
123 {}
124
125 virtual void init();
126
127 virtual Tick
128 recvResponse(PacketPtr pkt)
129 {
130 panic("recvResponse not implemented.\n");
131 return 0;
132 }
133};
134
135} // namespace X86ISA
136
137#endif //__DEV_X86_INTDEV_HH__