1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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44#define __DEV_X86_INTDEV_HH__
45
46#include <cassert>
47#include <list>
48#include <string>
49
50#include "arch/x86/intmessage.hh"
51#include "arch/x86/x86_traits.hh"
52#include "mem/mem_object.hh"
53#include "mem/mport.hh"
54#include "params/X86IntLine.hh"
55#include "params/X86IntSinkPin.hh"
56#include "params/X86IntSourcePin.hh"
57#include "sim/sim_object.hh"
58
59namespace X86ISA {
60
61typedef std::list<int> ApicList;
62
63class IntDevice
64{
65 protected:
66 class IntSlavePort : public MessageSlavePort
67 {
68 IntDevice * device;
69
70 public:
71 IntSlavePort(const std::string& _name, MemObject* _parent,
72 IntDevice* dev) :
73 MessageSlavePort(_name, _parent), device(dev)
74 {
75 }
76
77 AddrRangeList getAddrRanges() const
78 {
79 return device->getIntAddrRange();

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87 }
88 };
89
90 class IntMasterPort : public MessageMasterPort
91 {
92 IntDevice* device;
93 Tick latency;
94 public:
95 IntMasterPort(const std::string& _name, MemObject* _parent,
96 IntDevice* dev, Tick _latency) :
97 MessageMasterPort(_name, _parent), device(dev), latency(_latency)
98 {
99 }
100
101 Tick recvResponse(PacketPtr pkt)
102 {
103 return device->recvResponse(pkt);
104 }
105
106 // This is x86 focused, so if this class becomes generic, this would
107 // need to be moved into a subclass.
108 void sendMessage(ApicList apics,
109 TriggerIntMessage message, bool timing);
110 };
111
112 IntMasterPort intMasterPort;
113
114 public:
115 IntDevice(MemObject * parent, Tick latency = 0) :
116 intMasterPort(parent->name() + ".int_master", parent, this, latency)
117 {
118 }
119
120 virtual ~IntDevice()
121 {}
122
123 virtual void init();

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