1/* 2 * Copyright (c) 2012 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 37 unchanged lines hidden (view full) --- 46X86ISA::IntDev::IntMasterPort::sendMessage(ApicList apics, 47 TriggerIntMessage message, 48 bool timing) 49{ 50 ApicList::iterator apicIt; 51 for (apicIt = apics.begin(); apicIt != apics.end(); apicIt++) { 52 PacketPtr pkt = buildIntRequest(*apicIt, message); 53 if (timing) { |
54 schedTimingReq(pkt, curTick() + latency); |
55 // The target handles cleaning up the packet in timing mode. 56 } else { 57 // ignore the latency involved in the atomic transaction 58 sendAtomic(pkt); 59 assert(pkt->isResponse()); 60 // also ignore the latency in handling the response 61 recvResponse(pkt); 62 delete pkt->req; --- 30 unchanged lines hidden --- |