1/*
| 1/*
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| 2 * Copyright (c) 2012 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 *
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2 * Copyright (c) 2008 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Gabe Black 29 */ 30 31#include "dev/x86/intdev.hh" 32 33void
| 14 * Copyright (c) 2008 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Gabe Black 41 */ 42 43#include "dev/x86/intdev.hh" 44 45void
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34X86ISA::IntDev::IntPort::sendMessage(ApicList apics, 35 TriggerIntMessage message, bool timing)
| 46X86ISA::IntDev::IntPort::sendMessage(ApicList apics, TriggerIntMessage message, 47 bool timing)
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36{ 37 ApicList::iterator apicIt; 38 for (apicIt = apics.begin(); apicIt != apics.end(); apicIt++) { 39 PacketPtr pkt = buildIntRequest(*apicIt, message); 40 if (timing) {
| 48{ 49 ApicList::iterator apicIt; 50 for (apicIt = apics.begin(); apicIt != apics.end(); apicIt++) { 51 PacketPtr pkt = buildIntRequest(*apicIt, message); 52 if (timing) {
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41 sendMessageTiming(pkt, latency);
| 53 schedSendTiming(pkt, curTick() + latency);
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42 // The target handles cleaning up the packet in timing mode. 43 } else {
| 54 // The target handles cleaning up the packet in timing mode. 55 } else {
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44 sendMessageAtomic(pkt);
| 56 // ignore the latency involved in the atomic transaction 57 sendAtomic(pkt); 58 assert(pkt->isResponse()); 59 // also ignore the latency in handling the response 60 recvResponse(pkt);
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45 delete pkt->req; 46 delete pkt; 47 } 48 } 49} 50 51void 52X86ISA::IntDev::init() 53{ 54 if (!intPort.isConnected()) { 55 panic("Int port not connected to anything!"); 56 } 57 intPort.sendRangeChange(); 58} 59 60X86ISA::IntSourcePin * 61X86IntSourcePinParams::create() 62{ 63 return new X86ISA::IntSourcePin(this); 64} 65 66X86ISA::IntSinkPin * 67X86IntSinkPinParams::create() 68{ 69 return new X86ISA::IntSinkPin(this); 70} 71 72X86ISA::IntLine * 73X86IntLineParams::create() 74{ 75 return new X86ISA::IntLine(this); 76}
| 61 delete pkt->req; 62 delete pkt; 63 } 64 } 65} 66 67void 68X86ISA::IntDev::init() 69{ 70 if (!intPort.isConnected()) { 71 panic("Int port not connected to anything!"); 72 } 73 intPort.sendRangeChange(); 74} 75 76X86ISA::IntSourcePin * 77X86IntSourcePinParams::create() 78{ 79 return new X86ISA::IntSourcePin(this); 80} 81 82X86ISA::IntSinkPin * 83X86IntSinkPinParams::create() 84{ 85 return new X86ISA::IntSinkPin(this); 86} 87 88X86ISA::IntLine * 89X86IntLineParams::create() 90{ 91 return new X86ISA::IntLine(this); 92}
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