1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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34#include "dev/io_device.hh"
35#include "dev/x86/intdev.hh"
36#include "params/I8259.hh"
37#include "enums/X86I8259CascadeMode.hh"
38
39namespace X86ISA
40{
41
42class I82094AA;
43
44class I8259 : public BasicPioDevice, public IntDev
45{
46 protected:
47 static const int NumLines = 8;
48
49 Tick latency;
50 IntPin *output;
51 Enums::X86I8259CascadeMode mode;
52 I8259 * slave;
53
54 // Interrupt Request Register
55 uint8_t IRR;
56 // In Service Register
57 uint8_t ISR;
58 // Interrupt Mask Register
59 uint8_t IMR;
60

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77 typedef I8259Params Params;
78
79 const Params *
80 params() const
81 {
82 return dynamic_cast<const Params *>(_params);
83 }
84
80 I8259(Params * p) : BasicPioDevice(p), IntDev(this),
81 latency(p->pio_latency), output(p->output),
82 mode(p->mode), IRR(0), ISR(0), IMR(0),
83 vectorOffset(0), readIRR(true), initControlWord(0)
85 I8259(Params * p);
86
87 void
88 setSlave(I8259 * _slave)
89 {
85 pioSize = 2;
90 slave = _slave;
91 }
92
93 Tick read(PacketPtr pkt);
89
94 Tick write(PacketPtr pkt);
95
96 void signalInterrupt(int line);
97 int getVector();
98};
99
100}; // namespace X86ISA
101
102#endif //__DEV_X86_I8259_HH__