1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 */
30
31#ifndef __DEV_X86_I8259_HH__
32#define __DEV_X86_I8259_HH__
33
34#include "dev/io_device.hh"
35#include "dev/x86/intdev.hh"
36#include "params/I8259.hh"
37#include "enums/X86I8259CascadeMode.hh"
38
39namespace X86ISA
40{
41
42class I82094AA;
43
44class I8259 : public BasicPioDevice, public IntDev
45{
46 protected:
47 static const int NumLines = 8;
48
49 Tick latency;
50 IntPin *output;
51 Enums::X86I8259CascadeMode mode;
52 I8259 * slave;
53
54 // Interrupt Request Register
55 uint8_t IRR;
56 // In Service Register
57 uint8_t ISR;
58 // Interrupt Mask Register
59 uint8_t IMR;
60
61 // The higher order bits of the vector to return
62 uint8_t vectorOffset;
63
64 bool cascadeMode;
65 // A bit vector of lines with slaves attached, or the slave id, depending
66 // on if this is a master or slave PIC.
67 uint8_t cascadeBits;
68
69 bool edgeTriggered;
70 bool readIRR;
71
72 // State machine information for reading in initialization control words.
73 bool expectICW4;
74 int initControlWord;
75
| 1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 */
30
31#ifndef __DEV_X86_I8259_HH__
32#define __DEV_X86_I8259_HH__
33
34#include "dev/io_device.hh"
35#include "dev/x86/intdev.hh"
36#include "params/I8259.hh"
37#include "enums/X86I8259CascadeMode.hh"
38
39namespace X86ISA
40{
41
42class I82094AA;
43
44class I8259 : public BasicPioDevice, public IntDev
45{
46 protected:
47 static const int NumLines = 8;
48
49 Tick latency;
50 IntPin *output;
51 Enums::X86I8259CascadeMode mode;
52 I8259 * slave;
53
54 // Interrupt Request Register
55 uint8_t IRR;
56 // In Service Register
57 uint8_t ISR;
58 // Interrupt Mask Register
59 uint8_t IMR;
60
61 // The higher order bits of the vector to return
62 uint8_t vectorOffset;
63
64 bool cascadeMode;
65 // A bit vector of lines with slaves attached, or the slave id, depending
66 // on if this is a master or slave PIC.
67 uint8_t cascadeBits;
68
69 bool edgeTriggered;
70 bool readIRR;
71
72 // State machine information for reading in initialization control words.
73 bool expectICW4;
74 int initControlWord;
75
|