1/* 2 * Copyright (c) 2004-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Gabe Black 29 */ 30 31#ifndef __DEV_X86_I8259_HH__ 32#define __DEV_X86_I8259_HH__ 33 34#include "dev/io_device.hh" 35#include "dev/x86/intdev.hh" 36#include "params/I8259.hh" 37#include "enums/X86I8259CascadeMode.hh" 38 39namespace X86ISA 40{ 41
| 1/* 2 * Copyright (c) 2004-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Gabe Black 29 */ 30 31#ifndef __DEV_X86_I8259_HH__ 32#define __DEV_X86_I8259_HH__ 33 34#include "dev/io_device.hh" 35#include "dev/x86/intdev.hh" 36#include "params/I8259.hh" 37#include "enums/X86I8259CascadeMode.hh" 38 39namespace X86ISA 40{ 41
|
| 42class I82094AA; 43
|
42class I8259 : public BasicPioDevice, public IntDev 43{ 44 protected:
| 44class I8259 : public BasicPioDevice, public IntDev 45{ 46 protected:
|
| 47 static const int NumLines = 8; 48
|
45 Tick latency; 46 IntPin *output; 47 Enums::X86I8259CascadeMode mode;
| 49 Tick latency; 50 IntPin *output; 51 Enums::X86I8259CascadeMode mode;
|
| 52 I8259 * slave;
|
48 49 // Interrupt Request Register 50 uint8_t IRR; 51 // In Service Register 52 uint8_t ISR; 53 // Interrupt Mask Register 54 uint8_t IMR; 55 56 // The higher order bits of the vector to return 57 uint8_t vectorOffset; 58 59 bool cascadeMode; 60 // A bit vector of lines with slaves attached, or the slave id, depending 61 // on if this is a master or slave PIC. 62 uint8_t cascadeBits; 63 64 bool edgeTriggered; 65 bool readIRR; 66 67 // State machine information for reading in initialization control words. 68 bool expectICW4; 69 int initControlWord; 70 71 public: 72 typedef I8259Params Params; 73 74 const Params * 75 params() const 76 { 77 return dynamic_cast<const Params *>(_params); 78 } 79
| 53 54 // Interrupt Request Register 55 uint8_t IRR; 56 // In Service Register 57 uint8_t ISR; 58 // Interrupt Mask Register 59 uint8_t IMR; 60 61 // The higher order bits of the vector to return 62 uint8_t vectorOffset; 63 64 bool cascadeMode; 65 // A bit vector of lines with slaves attached, or the slave id, depending 66 // on if this is a master or slave PIC. 67 uint8_t cascadeBits; 68 69 bool edgeTriggered; 70 bool readIRR; 71 72 // State machine information for reading in initialization control words. 73 bool expectICW4; 74 int initControlWord; 75 76 public: 77 typedef I8259Params Params; 78 79 const Params * 80 params() const 81 { 82 return dynamic_cast<const Params *>(_params); 83 } 84
|
80 I8259(Params * p) : BasicPioDevice(p), IntDev(this), 81 latency(p->pio_latency), output(p->output), 82 mode(p->mode), IRR(0), ISR(0), IMR(0), 83 vectorOffset(0), readIRR(true), initControlWord(0)
| 85 I8259(Params * p); 86 87 void 88 setSlave(I8259 * _slave)
|
84 {
| 89 {
|
85 pioSize = 2;
| 90 slave = _slave;
|
86 } 87 88 Tick read(PacketPtr pkt);
| 91 } 92 93 Tick read(PacketPtr pkt);
|
89
| |
90 Tick write(PacketPtr pkt); 91 92 void signalInterrupt(int line);
| 94 Tick write(PacketPtr pkt); 95 96 void signalInterrupt(int line);
|
| 97 int getVector();
|
93}; 94 95}; // namespace X86ISA 96 97#endif //__DEV_X86_I8259_HH__
| 98}; 99 100}; // namespace X86ISA 101 102#endif //__DEV_X86_I8259_HH__
|