1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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34#include "dev/io_device.hh"
35#include "dev/x86/intdev.hh"
36#include "params/I8259.hh"
37#include "enums/X86I8259CascadeMode.hh"
38
39namespace X86ISA
40{
41
42class I8259 : public BasicPioDevice, public IntDev
43{
44 protected:
45 Tick latency;
46 IntPin *output;
47 Enums::X86I8259CascadeMode mode;
48
49 // Interrupt Request Register
50 uint8_t IRR;
51 // In Service Register
52 uint8_t ISR;
53 // Interrupt Mask Register
54 uint8_t IMR;
55

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72 typedef I8259Params Params;
73
74 const Params *
75 params() const
76 {
77 return dynamic_cast<const Params *>(_params);
78 }
79
80 I8259(Params * p) : BasicPioDevice(p), IntDev(this),
81 latency(p->pio_latency), output(p->output),
82 mode(p->mode), IRR(0), ISR(0), IMR(0),
83 vectorOffset(0), readIRR(true), initControlWord(0)
84 {
85 pioSize = 2;
86 }
87
88 Tick read(PacketPtr pkt);
89
90 Tick write(PacketPtr pkt);
91
92 void signalInterrupt(int line);
93};
94
95}; // namespace X86ISA
96
97#endif //__DEV_X86_I8259_HH__