34
35X86ISA::I8259::I8259(Params * p) : BasicPioDevice(p), IntDev(this),
36 latency(p->pio_latency), output(p->output),
37 mode(p->mode), slave(NULL),
38 IRR(0), ISR(0), IMR(0),
39 readIRR(true), initControlWord(0), autoEOI(false)
40{
41 if (output) {
42 I8259 * master;
43 master = dynamic_cast<I8259 *>(output->getDevice());
44 if (master)
45 master->setSlave(this);
46 I82094AA * ioApic;
47 ioApic = dynamic_cast<I82094AA *>(output->getDevice());
48 if (ioApic)
49 ioApic->setExtIntPic(this);
50 }
51 pioSize = 2;
52}
53
54Tick
55X86ISA::I8259::read(PacketPtr pkt)
56{
57 assert(pkt->getSize() == 1);
58 switch(pkt->getAddr() - pioAddr)
59 {
60 case 0x0:
61 if (readIRR) {
62 DPRINTF(I8259, "Reading IRR as %#x.\n", IRR);
63 pkt->set(IRR);
64 } else {
65 DPRINTF(I8259, "Reading ISR as %#x.\n", ISR);
66 pkt->set(ISR);
67 }
68 break;
69 case 0x1:
70 DPRINTF(I8259, "Reading IMR as %#x.\n", IMR);
71 pkt->set(IMR);
72 break;
73 }
74 return latency;
75}
76
77Tick
78X86ISA::I8259::write(PacketPtr pkt)
79{
80 assert(pkt->getSize() == 1);
81 uint8_t val = pkt->get<uint8_t>();
82 switch (pkt->getAddr() - pioAddr) {
83 case 0x0:
84 if (bits(val, 4)) {
85 DPRINTF(I8259, "Received initialization command word 1.\n");
86 IMR = 0;
87 edgeTriggered = bits(val, 3);
88 DPRINTF(I8259, "%s triggered mode.\n",
89 edgeTriggered ? "Edge" : "Level");
90 cascadeMode = !bits(val, 1);
91 DPRINTF(I8259, "%s mode.\n",
92 cascadeMode ? "Cascade" : "Single");
93 expectICW4 = bits(val, 0);
94 if (!expectICW4) {
95 autoEOI = false;
96 }
97 initControlWord = 1;
98 DPRINTF(I8259, "Expecting %d more bytes.\n", expectICW4 ? 3 : 2);
99 } else if (bits(val, 4, 3) == 0) {
100 DPRINTF(I8259, "Received operation command word 2.\n");
101 switch (bits(val, 7, 5)) {
102 case 0x0:
103 DPRINTF(I8259,
104 "Subcommand: Rotate in auto-EOI mode (clear).\n");
105 break;
106 case 0x1:
107 {
108 int line = findMsbSet(ISR);
109 DPRINTF(I8259, "Subcommand: Nonspecific EOI on line %d.\n",
110 line);
111 handleEOI(line);
112 }
113 break;
114 case 0x2:
115 DPRINTF(I8259, "Subcommand: No operation.\n");
116 break;
117 case 0x3:
118 {
119 int line = bits(val, 2, 0);
120 DPRINTF(I8259, "Subcommand: Specific EIO on line %d.\n",
121 line);
122 handleEOI(line);
123 }
124 break;
125 case 0x4:
126 DPRINTF(I8259, "Subcommand: Rotate in auto-EOI mode (set).\n");
127 break;
128 case 0x5:
129 DPRINTF(I8259, "Subcommand: Rotate on nonspecific EOI.\n");
130 break;
131 case 0x6:
132 DPRINTF(I8259, "Subcommand: Set priority command.\n");
133 DPRINTF(I8259, "Lowest: IRQ%d Highest IRQ%d.\n",
134 bits(val, 2, 0), (bits(val, 2, 0) + 1) % 8);
135 break;
136 case 0x7:
137 DPRINTF(I8259, "Subcommand: Rotate on specific EOI.\n");
138 DPRINTF(I8259, "Lowest: IRQ%d Highest IRQ%d.\n",
139 bits(val, 2, 0), (bits(val, 2, 0) + 1) % 8);
140 break;
141 }
142 } else if (bits(val, 4, 3) == 1) {
143 DPRINTF(I8259, "Received operation command word 3.\n");
144 if (bits(val, 7)) {
145 DPRINTF(I8259, "%s special mask mode.\n",
146 bits(val, 6) ? "Set" : "Clear");
147 }
148 if (bits(val, 1)) {
149 readIRR = bits(val, 0);
150 DPRINTF(I8259, "Read %s.\n", readIRR ? "IRR" : "ISR");
151 }
152 }
153 break;
154 case 0x1:
155 switch (initControlWord) {
156 case 0x0:
157 DPRINTF(I8259, "Received operation command word 1.\n");
158 DPRINTF(I8259, "Wrote IMR value %#x.\n", val);
159 IMR = val;
160 break;
161 case 0x1:
162 DPRINTF(I8259, "Received initialization command word 2.\n");
163 vectorOffset = val & ~mask(3);
164 DPRINTF(I8259, "Responsible for vectors %#x-%#x.\n",
165 vectorOffset, vectorOffset | mask(3));
166 if (cascadeMode) {
167 initControlWord++;
168 } else {
169 cascadeBits = 0;
170 initControlWord = 0;
171 }
172 break;
173 case 0x2:
174 DPRINTF(I8259, "Received initialization command word 3.\n");
175 if (mode == Enums::I8259Master) {
176 DPRINTF(I8259, "Slaves attached to IRQs:%s%s%s%s%s%s%s%s\n",
177 bits(val, 0) ? " 0" : "",
178 bits(val, 1) ? " 1" : "",
179 bits(val, 2) ? " 2" : "",
180 bits(val, 3) ? " 3" : "",
181 bits(val, 4) ? " 4" : "",
182 bits(val, 5) ? " 5" : "",
183 bits(val, 6) ? " 6" : "",
184 bits(val, 7) ? " 7" : "");
185 cascadeBits = val;
186 } else {
187 DPRINTF(I8259, "Slave ID is %d.\n", val & mask(3));
188 cascadeBits = val & mask(3);
189 }
190 if (expectICW4)
191 initControlWord++;
192 else
193 initControlWord = 0;
194 break;
195 case 0x3:
196 DPRINTF(I8259, "Received initialization command word 4.\n");
197 if (bits(val, 4)) {
198 DPRINTF(I8259, "Special fully nested mode.\n");
199 } else {
200 DPRINTF(I8259, "Not special fully nested mode.\n");
201 }
202 if (bits(val, 3) == 0) {
203 DPRINTF(I8259, "Nonbuffered.\n");
204 } else if (bits(val, 2) == 0) {
205 DPRINTF(I8259, "Buffered.\n");
206 } else {
207 DPRINTF(I8259, "Unrecognized buffer mode.\n");
208 }
209 autoEOI = bits(val, 1);
210 DPRINTF(I8259, "%s End Of Interrupt.\n",
211 autoEOI ? "Automatic" : "Normal");
212
213 DPRINTF(I8259, "%s mode.\n", bits(val, 0) ? "80x86" : "MCX-80/85");
214 initControlWord = 0;
215 break;
216 }
217 break;
218 }
219 return latency;
220}
221
222void
223X86ISA::I8259::handleEOI(int line)
224{
225 ISR &= ~(1 << line);
226 // There may be an interrupt that was waiting which can
227 // now be sent.
228 if (IRR)
229 requestInterrupt(findMsbSet(IRR));
230}
231
232void
233X86ISA::I8259::requestInterrupt(int line)
234{
235 if (bits(ISR, 7, line) == 0) {
236 if (output) {
237 DPRINTF(I8259, "Propogating interrupt.\n");
238 output->signalInterrupt();
239 } else {
240 warn("Received interrupt but didn't have "
241 "anyone to tell about it.\n");
242 }
243 }
244}
245
246void
247X86ISA::I8259::signalInterrupt(int line)
248{
249 DPRINTF(I8259, "Interrupt raised on line %d.\n", line);
250 if (line >= NumLines)
251 fatal("Line number %d doesn't exist. The max is %d.\n",
252 line, NumLines - 1);
253 if (bits(IMR, line)) {
254 DPRINTF(I8259, "Interrupt %d was masked.\n", line);
255 } else {
256 IRR |= 1 << line;
257 requestInterrupt(line);
258 }
259}
260
261int
262X86ISA::I8259::getVector()
263{
264 /*
265 * This code only handles one slave. Since that's how the PC platform
266 * always uses the 8259 PIC, there shouldn't be any need for more. If
267 * there -is- a need for more for some reason, "slave" can become a
268 * vector of slaves.
269 */
270 int line = findMsbSet(IRR);
271 IRR &= ~(1 << line);
272 DPRINTF(I8259, "Interrupt %d was accepted.\n", line);
273 if (autoEOI) {
274 handleEOI(line);
275 } else {
276 ISR |= 1 << line;
277 }
278 if (slave && bits(cascadeBits, line)) {
279 DPRINTF(I8259, "Interrupt was from slave who will "
280 "provide the vector.\n");
281 return slave->getVector();
282 }
283 return line | vectorOffset;
284}
285
286X86ISA::I8259 *
287I8259Params::create()
288{
289 return new X86ISA::I8259(this);
290}
| 36
37X86ISA::I8259::I8259(Params * p) : BasicPioDevice(p), IntDev(this),
38 latency(p->pio_latency), output(p->output),
39 mode(p->mode), slave(NULL),
40 IRR(0), ISR(0), IMR(0),
41 readIRR(true), initControlWord(0), autoEOI(false)
42{
43 if (output) {
44 I8259 * master;
45 master = dynamic_cast<I8259 *>(output->getDevice());
46 if (master)
47 master->setSlave(this);
48 I82094AA * ioApic;
49 ioApic = dynamic_cast<I82094AA *>(output->getDevice());
50 if (ioApic)
51 ioApic->setExtIntPic(this);
52 }
53 pioSize = 2;
54}
55
56Tick
57X86ISA::I8259::read(PacketPtr pkt)
58{
59 assert(pkt->getSize() == 1);
60 switch(pkt->getAddr() - pioAddr)
61 {
62 case 0x0:
63 if (readIRR) {
64 DPRINTF(I8259, "Reading IRR as %#x.\n", IRR);
65 pkt->set(IRR);
66 } else {
67 DPRINTF(I8259, "Reading ISR as %#x.\n", ISR);
68 pkt->set(ISR);
69 }
70 break;
71 case 0x1:
72 DPRINTF(I8259, "Reading IMR as %#x.\n", IMR);
73 pkt->set(IMR);
74 break;
75 }
76 return latency;
77}
78
79Tick
80X86ISA::I8259::write(PacketPtr pkt)
81{
82 assert(pkt->getSize() == 1);
83 uint8_t val = pkt->get<uint8_t>();
84 switch (pkt->getAddr() - pioAddr) {
85 case 0x0:
86 if (bits(val, 4)) {
87 DPRINTF(I8259, "Received initialization command word 1.\n");
88 IMR = 0;
89 edgeTriggered = bits(val, 3);
90 DPRINTF(I8259, "%s triggered mode.\n",
91 edgeTriggered ? "Edge" : "Level");
92 cascadeMode = !bits(val, 1);
93 DPRINTF(I8259, "%s mode.\n",
94 cascadeMode ? "Cascade" : "Single");
95 expectICW4 = bits(val, 0);
96 if (!expectICW4) {
97 autoEOI = false;
98 }
99 initControlWord = 1;
100 DPRINTF(I8259, "Expecting %d more bytes.\n", expectICW4 ? 3 : 2);
101 } else if (bits(val, 4, 3) == 0) {
102 DPRINTF(I8259, "Received operation command word 2.\n");
103 switch (bits(val, 7, 5)) {
104 case 0x0:
105 DPRINTF(I8259,
106 "Subcommand: Rotate in auto-EOI mode (clear).\n");
107 break;
108 case 0x1:
109 {
110 int line = findMsbSet(ISR);
111 DPRINTF(I8259, "Subcommand: Nonspecific EOI on line %d.\n",
112 line);
113 handleEOI(line);
114 }
115 break;
116 case 0x2:
117 DPRINTF(I8259, "Subcommand: No operation.\n");
118 break;
119 case 0x3:
120 {
121 int line = bits(val, 2, 0);
122 DPRINTF(I8259, "Subcommand: Specific EIO on line %d.\n",
123 line);
124 handleEOI(line);
125 }
126 break;
127 case 0x4:
128 DPRINTF(I8259, "Subcommand: Rotate in auto-EOI mode (set).\n");
129 break;
130 case 0x5:
131 DPRINTF(I8259, "Subcommand: Rotate on nonspecific EOI.\n");
132 break;
133 case 0x6:
134 DPRINTF(I8259, "Subcommand: Set priority command.\n");
135 DPRINTF(I8259, "Lowest: IRQ%d Highest IRQ%d.\n",
136 bits(val, 2, 0), (bits(val, 2, 0) + 1) % 8);
137 break;
138 case 0x7:
139 DPRINTF(I8259, "Subcommand: Rotate on specific EOI.\n");
140 DPRINTF(I8259, "Lowest: IRQ%d Highest IRQ%d.\n",
141 bits(val, 2, 0), (bits(val, 2, 0) + 1) % 8);
142 break;
143 }
144 } else if (bits(val, 4, 3) == 1) {
145 DPRINTF(I8259, "Received operation command word 3.\n");
146 if (bits(val, 7)) {
147 DPRINTF(I8259, "%s special mask mode.\n",
148 bits(val, 6) ? "Set" : "Clear");
149 }
150 if (bits(val, 1)) {
151 readIRR = bits(val, 0);
152 DPRINTF(I8259, "Read %s.\n", readIRR ? "IRR" : "ISR");
153 }
154 }
155 break;
156 case 0x1:
157 switch (initControlWord) {
158 case 0x0:
159 DPRINTF(I8259, "Received operation command word 1.\n");
160 DPRINTF(I8259, "Wrote IMR value %#x.\n", val);
161 IMR = val;
162 break;
163 case 0x1:
164 DPRINTF(I8259, "Received initialization command word 2.\n");
165 vectorOffset = val & ~mask(3);
166 DPRINTF(I8259, "Responsible for vectors %#x-%#x.\n",
167 vectorOffset, vectorOffset | mask(3));
168 if (cascadeMode) {
169 initControlWord++;
170 } else {
171 cascadeBits = 0;
172 initControlWord = 0;
173 }
174 break;
175 case 0x2:
176 DPRINTF(I8259, "Received initialization command word 3.\n");
177 if (mode == Enums::I8259Master) {
178 DPRINTF(I8259, "Slaves attached to IRQs:%s%s%s%s%s%s%s%s\n",
179 bits(val, 0) ? " 0" : "",
180 bits(val, 1) ? " 1" : "",
181 bits(val, 2) ? " 2" : "",
182 bits(val, 3) ? " 3" : "",
183 bits(val, 4) ? " 4" : "",
184 bits(val, 5) ? " 5" : "",
185 bits(val, 6) ? " 6" : "",
186 bits(val, 7) ? " 7" : "");
187 cascadeBits = val;
188 } else {
189 DPRINTF(I8259, "Slave ID is %d.\n", val & mask(3));
190 cascadeBits = val & mask(3);
191 }
192 if (expectICW4)
193 initControlWord++;
194 else
195 initControlWord = 0;
196 break;
197 case 0x3:
198 DPRINTF(I8259, "Received initialization command word 4.\n");
199 if (bits(val, 4)) {
200 DPRINTF(I8259, "Special fully nested mode.\n");
201 } else {
202 DPRINTF(I8259, "Not special fully nested mode.\n");
203 }
204 if (bits(val, 3) == 0) {
205 DPRINTF(I8259, "Nonbuffered.\n");
206 } else if (bits(val, 2) == 0) {
207 DPRINTF(I8259, "Buffered.\n");
208 } else {
209 DPRINTF(I8259, "Unrecognized buffer mode.\n");
210 }
211 autoEOI = bits(val, 1);
212 DPRINTF(I8259, "%s End Of Interrupt.\n",
213 autoEOI ? "Automatic" : "Normal");
214
215 DPRINTF(I8259, "%s mode.\n", bits(val, 0) ? "80x86" : "MCX-80/85");
216 initControlWord = 0;
217 break;
218 }
219 break;
220 }
221 return latency;
222}
223
224void
225X86ISA::I8259::handleEOI(int line)
226{
227 ISR &= ~(1 << line);
228 // There may be an interrupt that was waiting which can
229 // now be sent.
230 if (IRR)
231 requestInterrupt(findMsbSet(IRR));
232}
233
234void
235X86ISA::I8259::requestInterrupt(int line)
236{
237 if (bits(ISR, 7, line) == 0) {
238 if (output) {
239 DPRINTF(I8259, "Propogating interrupt.\n");
240 output->signalInterrupt();
241 } else {
242 warn("Received interrupt but didn't have "
243 "anyone to tell about it.\n");
244 }
245 }
246}
247
248void
249X86ISA::I8259::signalInterrupt(int line)
250{
251 DPRINTF(I8259, "Interrupt raised on line %d.\n", line);
252 if (line >= NumLines)
253 fatal("Line number %d doesn't exist. The max is %d.\n",
254 line, NumLines - 1);
255 if (bits(IMR, line)) {
256 DPRINTF(I8259, "Interrupt %d was masked.\n", line);
257 } else {
258 IRR |= 1 << line;
259 requestInterrupt(line);
260 }
261}
262
263int
264X86ISA::I8259::getVector()
265{
266 /*
267 * This code only handles one slave. Since that's how the PC platform
268 * always uses the 8259 PIC, there shouldn't be any need for more. If
269 * there -is- a need for more for some reason, "slave" can become a
270 * vector of slaves.
271 */
272 int line = findMsbSet(IRR);
273 IRR &= ~(1 << line);
274 DPRINTF(I8259, "Interrupt %d was accepted.\n", line);
275 if (autoEOI) {
276 handleEOI(line);
277 } else {
278 ISR |= 1 << line;
279 }
280 if (slave && bits(cascadeBits, line)) {
281 DPRINTF(I8259, "Interrupt was from slave who will "
282 "provide the vector.\n");
283 return slave->getVector();
284 }
285 return line | vectorOffset;
286}
287
288X86ISA::I8259 *
289I8259Params::create()
290{
291 return new X86ISA::I8259(this);
292}
|