i82094aa.hh (11144:90eeefe7e341) i82094aa.hh (11168:f98eb2da15a4)
1/*
2 * Copyright (c) 2008 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 91 unchanged lines hidden (view full) ---

100 AddrRangeList getIntAddrRange() const;
101
102 void writeReg(uint8_t offset, uint32_t value);
103 uint32_t readReg(uint8_t offset);
104
105 BaseMasterPort &getMasterPort(const std::string &if_name,
106 PortID idx = InvalidPortID);
107
1/*
2 * Copyright (c) 2008 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 91 unchanged lines hidden (view full) ---

100 AddrRangeList getIntAddrRange() const;
101
102 void writeReg(uint8_t offset, uint32_t value);
103 uint32_t readReg(uint8_t offset);
104
105 BaseMasterPort &getMasterPort(const std::string &if_name,
106 PortID idx = InvalidPortID);
107
108 Tick recvResponse(PacketPtr pkt) M5_ATTR_OVERRIDE;
108 Tick recvResponse(PacketPtr pkt) override;
109
110 void signalInterrupt(int line);
111 void raiseInterruptPin(int number);
112 void lowerInterruptPin(int number);
113
109
110 void signalInterrupt(int line);
111 void raiseInterruptPin(int number);
112 void lowerInterruptPin(int number);
113
114 void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
115 void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
114 void serialize(CheckpointOut &cp) const override;
115 void unserialize(CheckpointIn &cp) override;
116};
117
118} // namespace X86ISA
119
120#endif //__DEV_X86_SOUTH_BRIDGE_I8254_HH__
116};
117
118} // namespace X86ISA
119
120#endif //__DEV_X86_SOUTH_BRIDGE_I8254_HH__