i82094aa.cc (9524:d6ffa982a68b) i82094aa.cc (9805:a4339e26b429)
1/*
2 * Copyright (c) 2008 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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33#include "cpu/base.hh"
34#include "debug/I82094AA.hh"
35#include "dev/x86/i82094aa.hh"
36#include "dev/x86/i8259.hh"
37#include "mem/packet.hh"
38#include "mem/packet_access.hh"
39#include "sim/system.hh"
40
1/*
2 * Copyright (c) 2008 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 24 unchanged lines hidden (view full) ---

33#include "cpu/base.hh"
34#include "debug/I82094AA.hh"
35#include "dev/x86/i82094aa.hh"
36#include "dev/x86/i8259.hh"
37#include "mem/packet.hh"
38#include "mem/packet_access.hh"
39#include "sim/system.hh"
40
41X86ISA::I82094AA::I82094AA(Params *p) : PioDevice(p),
42 IntDev(this, p->int_latency),
43 latency(p->pio_latency), pioAddr(p->pio_addr),
44 extIntPic(p->external_int_pic), lowestPriorityOffset(0)
41X86ISA::I82094AA::I82094AA(Params *p)
42 : BasicPioDevice(p), IntDev(this, p->int_latency),
43 extIntPic(p->external_int_pic), lowestPriorityOffset(0)
45{
46 // This assumes there's only one I/O APIC in the system and since the apic
47 // id is stored in a 8-bit field with 0xff meaning broadcast, the id must
48 // be less than 0xff
49
50 assert(p->apic_id < 0xff);
51 initialApicId = id = p->apic_id;
52 arbId = id;
53 regSel = 0;
54 RedirTableEntry entry = 0;
55 entry.mask = 1;
56 for (int i = 0; i < TableSize; i++) {
57 redirTable[i] = entry;
58 pinStates[i] = false;
59 }
44{
45 // This assumes there's only one I/O APIC in the system and since the apic
46 // id is stored in a 8-bit field with 0xff meaning broadcast, the id must
47 // be less than 0xff
48
49 assert(p->apic_id < 0xff);
50 initialApicId = id = p->apic_id;
51 arbId = id;
52 regSel = 0;
53 RedirTableEntry entry = 0;
54 entry.mask = 1;
55 for (int i = 0; i < TableSize; i++) {
56 redirTable[i] = entry;
57 pinStates[i] = false;
58 }
59
60 pioSize = 20;
60}
61
62void
63X86ISA::I82094AA::init()
64{
65 // The io apic must register its address ranges on both its pio port
66 // via the piodevice init() function and its int port that it inherited
67 // from IntDev. Note IntDev is not a SimObject itself.
68
61}
62
63void
64X86ISA::I82094AA::init()
65{
66 // The io apic must register its address ranges on both its pio port
67 // via the piodevice init() function and its int port that it inherited
68 // from IntDev. Note IntDev is not a SimObject itself.
69
69 PioDevice::init();
70 BasicPioDevice::init();
70 IntDev::init();
71}
72
71 IntDev::init();
72}
73
74BaseMasterPort &
75X86ISA::I82094AA::getMasterPort(const std::string &if_name, PortID idx)
76{
77 if (if_name == "int_master")
78 return intMasterPort;
79 return BasicPioDevice::getMasterPort(if_name, idx);
80}
81
82AddrRangeList
83X86ISA::I82094AA::getIntAddrRange() const
84{
85 AddrRangeList ranges;
86 ranges.push_back(RangeEx(x86InterruptAddress(initialApicId, 0),
87 x86InterruptAddress(initialApicId, 0) +
88 PhysAddrAPICRangeSize));
89 return ranges;
90}
91
73Tick
74X86ISA::I82094AA::read(PacketPtr pkt)
75{
76 assert(pkt->getSize() == 4);
77 Addr offset = pkt->getAddr() - pioAddr;
78 switch(offset) {
79 case 0:
80 pkt->set<uint32_t>(regSel);
81 break;
82 case 16:
83 pkt->set<uint32_t>(readReg(regSel));
84 break;
85 default:
86 panic("Illegal read from I/O APIC.\n");
87 }
88 pkt->makeAtomicResponse();
92Tick
93X86ISA::I82094AA::read(PacketPtr pkt)
94{
95 assert(pkt->getSize() == 4);
96 Addr offset = pkt->getAddr() - pioAddr;
97 switch(offset) {
98 case 0:
99 pkt->set<uint32_t>(regSel);
100 break;
101 case 16:
102 pkt->set<uint32_t>(readReg(regSel));
103 break;
104 default:
105 panic("Illegal read from I/O APIC.\n");
106 }
107 pkt->makeAtomicResponse();
89 return latency;
108 return pioDelay;
90}
91
92Tick
93X86ISA::I82094AA::write(PacketPtr pkt)
94{
95 assert(pkt->getSize() == 4);
96 Addr offset = pkt->getAddr() - pioAddr;
97 switch(offset) {
98 case 0:
99 regSel = pkt->get<uint32_t>();
100 break;
101 case 16:
102 writeReg(regSel, pkt->get<uint32_t>());
103 break;
104 default:
105 panic("Illegal write to I/O APIC.\n");
106 }
107 pkt->makeAtomicResponse();
109}
110
111Tick
112X86ISA::I82094AA::write(PacketPtr pkt)
113{
114 assert(pkt->getSize() == 4);
115 Addr offset = pkt->getAddr() - pioAddr;
116 switch(offset) {
117 case 0:
118 regSel = pkt->get<uint32_t>();
119 break;
120 case 16:
121 writeReg(regSel, pkt->get<uint32_t>());
122 break;
123 default:
124 panic("Illegal write to I/O APIC.\n");
125 }
126 pkt->makeAtomicResponse();
108 return latency;
127 return pioDelay;
109}
110
111void
112X86ISA::I82094AA::writeReg(uint8_t offset, uint32_t value)
113{
114 if (offset == 0x0) {
115 id = bits(value, 31, 24);
116 } else if (offset == 0x1) {

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129
130void
131X86ISA::I82094AA::writeReg(uint8_t offset, uint32_t value)
132{
133 if (offset == 0x0) {
134 id = bits(value, 31, 24);
135 } else if (offset == 0x1) {

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