i82094aa.cc (5654:340254de2031) i82094aa.cc (5657:7539092b28ac)
1/*
2 * Copyright (c) 2008 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 */
30
31#include "arch/x86/intmessage.hh"
32#include "dev/x86/i82094aa.hh"
1/*
2 * Copyright (c) 2008 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 */
30
31#include "arch/x86/intmessage.hh"
32#include "dev/x86/i82094aa.hh"
33#include "dev/x86/i8259.hh"
33#include "mem/packet.hh"
34#include "mem/packet_access.hh"
35#include "sim/system.hh"
36
37X86ISA::I82094AA::I82094AA(Params *p) : PioDevice(p), IntDev(this),
34#include "mem/packet.hh"
35#include "mem/packet_access.hh"
36#include "sim/system.hh"
37
38X86ISA::I82094AA::I82094AA(Params *p) : PioDevice(p), IntDev(this),
38 latency(p->pio_latency), pioAddr(p->pio_addr)
39 latency(p->pio_latency), pioAddr(p->pio_addr), extIntPic(NULL)
39{
40 // This assumes there's only one I/O APIC in the system
41 id = sys->getNumCPUs();
42 assert(id <= 0xf);
43 arbId = id;
44 regSel = 0;
45 RedirTableEntry entry = 0;
46 entry.mask = 1;

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140{
141 DPRINTF(I82094AA, "Received interrupt %d.\n", line);
142 assert(line < TableSize);
143 RedirTableEntry entry = redirTable[line];
144 if (entry.mask) {
145 DPRINTF(I82094AA, "Entry was masked.\n");
146 return;
147 } else {
40{
41 // This assumes there's only one I/O APIC in the system
42 id = sys->getNumCPUs();
43 assert(id <= 0xf);
44 arbId = id;
45 regSel = 0;
46 RedirTableEntry entry = 0;
47 entry.mask = 1;

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141{
142 DPRINTF(I82094AA, "Received interrupt %d.\n", line);
143 assert(line < TableSize);
144 RedirTableEntry entry = redirTable[line];
145 if (entry.mask) {
146 DPRINTF(I82094AA, "Entry was masked.\n");
147 return;
148 } else {
148 if (DTRACE(I82094AA)) {
149 if (DeliveryMode::isReserved(entry.deliveryMode)) {
150 fatal("Tried to use reserved delivery mode "
151 "for IO APIC entry %d.\n", line);
152 } else {
153 DPRINTF(I82094AA, "Delivery mode is: %s.\n",
154 DeliveryMode::names[entry.deliveryMode]);
155 }
156 DPRINTF(I82094AA, "Vector is %#x.\n", entry.vector);
157 }
158
159 TriggerIntMessage message;
160 message.destination = entry.dest;
149 TriggerIntMessage message;
150 message.destination = entry.dest;
161 message.vector = entry.vector;
151 if (entry.deliveryMode == DeliveryMode::ExtInt) {
152 assert(extIntPic);
153 message.vector = extIntPic->getVector();
154 } else {
155 message.vector = entry.vector;
156 }
162 message.deliveryMode = entry.deliveryMode;
163 message.destMode = entry.destMode;
164 message.level = entry.polarity;
165 message.trigger = entry.trigger;
166
157 message.deliveryMode = entry.deliveryMode;
158 message.destMode = entry.destMode;
159 message.level = entry.polarity;
160 message.trigger = entry.trigger;
161
162 if (DeliveryMode::isReserved(entry.deliveryMode)) {
163 fatal("Tried to use reserved delivery mode "
164 "for IO APIC entry %d.\n", line);
165 } else if (DTRACE(I82094AA)) {
166 DPRINTF(I82094AA, "Delivery mode is: %s.\n",
167 DeliveryMode::names[entry.deliveryMode]);
168 DPRINTF(I82094AA, "Vector is %#x.\n", message.vector);
169 }
170
167 if (entry.destMode == 0) {
168 DPRINTF(I82094AA,
169 "Sending interrupt to APIC ID %d.\n", entry.dest);
170 PacketPtr pkt = buildIntRequest(entry.dest, message);
171 if (sys->getMemoryMode() == Enums::timing)
172 intPort->sendMessageTiming(pkt, latency);
173 else if (sys->getMemoryMode() == Enums::atomic)
174 intPort->sendMessageAtomic(pkt);

--- 38 unchanged lines hidden --- 		171 if (entry.destMode == 0) {
172 DPRINTF(I82094AA,
173 "Sending interrupt to APIC ID %d.\n", entry.dest);
174 PacketPtr pkt = buildIntRequest(entry.dest, message);
175 if (sys->getMemoryMode() == Enums::timing)
176 intPort->sendMessageTiming(pkt, latency);
177 else if (sys->getMemoryMode() == Enums::atomic)
178 intPort->sendMessageAtomic(pkt);

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