i82094aa.cc (5643:2b1611137af4) i82094aa.cc (5651:7f0c8006c3d7)
1/*
2 * Copyright (c) 2008 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 14 unchanged lines hidden (view full) ---

23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 */
30
1/*
2 * Copyright (c) 2008 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 14 unchanged lines hidden (view full) ---

23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 */
30
31#include "arch/x86/intmessage.hh"
31#include "dev/x86/i82094aa.hh"
32#include "mem/packet.hh"
33#include "mem/packet_access.hh"
34#include "sim/system.hh"
35
32#include "dev/x86/i82094aa.hh"
33#include "mem/packet.hh"
34#include "mem/packet_access.hh"
35#include "sim/system.hh"
36
36X86ISA::I82094AA::I82094AA(Params *p) : PioDevice(p),
37X86ISA::I82094AA::I82094AA(Params *p) : PioDevice(p), IntDev(this),
37 latency(p->pio_latency), pioAddr(p->pio_addr)
38{
39 // This assumes there's only one I/O APIC in the system
40 id = sys->getNumCPUs();
41 assert(id <= 0xf);
42 arbId = id;
43 regSel = 0;
44 memset(redirTable, 0, sizeof(RedirTableEntry) * TableSize);

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135{
136 DPRINTF(I82094AA, "Received interrupt %d.\n", line);
137 assert(line < TableSize);
138 RedirTableEntry entry = redirTable[line];
139 if (entry.mask) {
140 DPRINTF(I82094AA, "Entry was masked.\n");
141 return;
142 } else {
38 latency(p->pio_latency), pioAddr(p->pio_addr)
39{
40 // This assumes there's only one I/O APIC in the system
41 id = sys->getNumCPUs();
42 assert(id <= 0xf);
43 arbId = id;
44 regSel = 0;
45 memset(redirTable, 0, sizeof(RedirTableEntry) * TableSize);

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136{
137 DPRINTF(I82094AA, "Received interrupt %d.\n", line);
138 assert(line < TableSize);
139 RedirTableEntry entry = redirTable[line];
140 if (entry.mask) {
141 DPRINTF(I82094AA, "Entry was masked.\n");
142 return;
143 } else {
144 if (DTRACE(I82094AA)) {
145 switch(entry.deliveryMode) {
146 case 0:
147 DPRINTF(I82094AA, "Delivery mode is: Fixed.\n");
148 break;
149 case 1:
150 DPRINTF(I82094AA, "Delivery mode is: Lowest Priority.\n");
151 break;
152 case 2:
153 DPRINTF(I82094AA, "Delivery mode is: SMI.\n");
154 break;
155 case 3:
156 fatal("Tried to use reserved delivery mode "
157 "for IO APIC entry %d.\n", line);
158 break;
159 case 4:
160 DPRINTF(I82094AA, "Delivery mode is: NMI.\n");
161 break;
162 case 5:
163 DPRINTF(I82094AA, "Delivery mode is: INIT.\n");
164 break;
165 case 6:
166 fatal("Tried to use reserved delivery mode "
167 "for IO APIC entry %d.\n", line);
168 break;
169 case 7:
170 DPRINTF(I82094AA, "Delivery mode is: ExtINT.\n");
171 break;
172 }
173 DPRINTF(I82094AA, "Vector is %#x.\n", entry.vector);
174 }
175
176 TriggerIntMessage message;
177 message.destination = entry.dest;
178 message.vector = entry.vector;
179 message.deliveryMode = entry.deliveryMode;
180 message.destMode = entry.destMode;
181
143 if (entry.destMode == 0) {
144 DPRINTF(I82094AA,
182 if (entry.destMode == 0) {
183 DPRINTF(I82094AA,
145 "Would send interrupt to APIC ID %d.\n", entry.dest);
184 "Sending interrupt to APIC ID %d.\n", entry.dest);
185 PacketPtr pkt = buildIntRequest(entry.dest, message);
186 if (sys->getMemoryMode() == Enums::timing)
187 intPort->sendMessageTiming(pkt, latency);
188 else if (sys->getMemoryMode() == Enums::atomic)
189 intPort->sendMessageAtomic(pkt);
190 else
191 panic("Unrecognized memory mode.\n");
146 } else {
192 } else {
147 DPRINTF(I82094AA, "Would send interrupts to APIC IDs:"
193 DPRINTF(I82094AA, "Sending interrupts to APIC IDs:"
148 "%s%s%s%s%s%s%s%s\n",
149 bits((int)entry.dest, 0) ? " 0": "",
150 bits((int)entry.dest, 1) ? " 1": "",
151 bits((int)entry.dest, 2) ? " 2": "",
152 bits((int)entry.dest, 3) ? " 3": "",
153 bits((int)entry.dest, 4) ? " 4": "",
154 bits((int)entry.dest, 5) ? " 5": "",
155 bits((int)entry.dest, 6) ? " 6": "",
156 bits((int)entry.dest, 7) ? " 7": ""
157 );
194 "%s%s%s%s%s%s%s%s\n",
195 bits((int)entry.dest, 0) ? " 0": "",
196 bits((int)entry.dest, 1) ? " 1": "",
197 bits((int)entry.dest, 2) ? " 2": "",
198 bits((int)entry.dest, 3) ? " 3": "",
199 bits((int)entry.dest, 4) ? " 4": "",
200 bits((int)entry.dest, 5) ? " 5": "",
201 bits((int)entry.dest, 6) ? " 6": "",
202 bits((int)entry.dest, 7) ? " 7": ""
203 );
204 uint8_t dests = entry.dest;
205 uint8_t id = 0;
206 while(dests) {
207 if (dests & 0x1) {
208 PacketPtr pkt = buildIntRequest(id, message);
209 if (sys->getMemoryMode() == Enums::timing)
210 intPort->sendMessageTiming(pkt, latency);
211 else if (sys->getMemoryMode() == Enums::atomic)
212 intPort->sendMessageAtomic(pkt);
213 else
214 panic("Unrecognized memory mode.\n");
215 }
216 dests >>= 1;
217 id++;
218 }
158 }
219 }
159 switch(entry.deliveryMode) {
160 case 0:
161 DPRINTF(I82094AA, "Delivery mode is: Fixed.\n");
162 break;
163 case 1:
164 DPRINTF(I82094AA, "Delivery mode is: Lowest Priority.\n");
165 break;
166 case 2:
167 DPRINTF(I82094AA, "Delivery mode is: SMI.\n");
168 break;
169 case 3:
170 fatal("Tried to use reserved delivery mode "
171 "for IO APIC entry %d.\n", line);
172 break;
173 case 4:
174 DPRINTF(I82094AA, "Delivery mode is: NMI.\n");
175 break;
176 case 5:
177 DPRINTF(I82094AA, "Delivery mode is: INIT.\n");
178 break;
179 case 6:
180 fatal("Tried to use reserved delivery mode "
181 "for IO APIC entry %d.\n", line);
182 break;
183 case 7:
184 DPRINTF(I82094AA, "Delivery mode is: ExtINT.\n");
185 break;
186 }
187 DPRINTF(I82094AA, "Vector is %#x.\n", entry.vector);
188 }
189}
190
191X86ISA::I82094AA *
192I82094AAParams::create()
193{
194 return new X86ISA::I82094AA(this);
195}
220 }
221}
222
223X86ISA::I82094AA *
224I82094AAParams::create()
225{
226 return new X86ISA::I82094AA(this);
227}