1/* 2 * Copyright (c) 2008 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Gabe Black 29 */ 30 31#include "arch/x86/intmessage.hh" 32#include "dev/x86/i82094aa.hh" 33#include "dev/x86/i8259.hh" 34#include "mem/packet.hh" 35#include "mem/packet_access.hh" 36#include "sim/system.hh" 37 38X86ISA::I82094AA::I82094AA(Params *p) : PioDevice(p), IntDev(this), 39 latency(p->pio_latency), pioAddr(p->pio_addr), 40 extIntPic(p->external_int_pic) 41{ 42 // This assumes there's only one I/O APIC in the system 43 id = sys->numContexts(); 44 assert(id <= 0xf); 45 arbId = id; 46 regSel = 0; 47 RedirTableEntry entry = 0; 48 entry.mask = 1; 49 for (int i = 0; i < TableSize; i++) { 50 redirTable[i] = entry; 51 pinStates[i] = false; 52 } 53} 54 55Tick 56X86ISA::I82094AA::read(PacketPtr pkt) 57{ 58 assert(pkt->getSize() == 4); 59 Addr offset = pkt->getAddr() - pioAddr; 60 switch(offset) { 61 case 0: 62 pkt->set<uint32_t>(regSel); 63 break; 64 case 16: 65 pkt->set<uint32_t>(readReg(regSel)); 66 break; 67 default: 68 panic("Illegal read from I/O APIC.\n"); 69 } 70 pkt->makeAtomicResponse(); 71 return latency; 72} 73 74Tick 75X86ISA::I82094AA::write(PacketPtr pkt) 76{ 77 assert(pkt->getSize() == 4); 78 Addr offset = pkt->getAddr() - pioAddr; 79 switch(offset) { 80 case 0: 81 regSel = pkt->get<uint32_t>(); 82 break; 83 case 16: 84 writeReg(regSel, pkt->get<uint32_t>()); 85 break; 86 default: 87 panic("Illegal write to I/O APIC.\n"); 88 } 89 pkt->makeAtomicResponse(); 90 return latency; 91} 92 93void 94X86ISA::I82094AA::writeReg(uint8_t offset, uint32_t value) 95{ 96 if (offset == 0x0) { 97 id = bits(value, 27, 24); 98 } else if (offset == 0x1) { 99 // The IOAPICVER register is read only. 100 } else if (offset == 0x2) { 101 arbId = bits(value, 27, 24); 102 } else if (offset >= 0x10 && offset <= (0x10 + TableSize * 2)) { 103 int index = (offset - 0x10) / 2; 104 if (offset % 2) { 105 redirTable[index].topDW = value; 106 redirTable[index].topReserved = 0; 107 } else { 108 redirTable[index].bottomDW = value; 109 redirTable[index].bottomReserved = 0; 110 } 111 } else { 112 warn("Access to undefined I/O APIC register %#x.\n", offset); 113 } 114 DPRINTF(I82094AA, 115 "Wrote %#x to I/O APIC register %#x .\n", value, offset); 116} 117 118uint32_t 119X86ISA::I82094AA::readReg(uint8_t offset) 120{ 121 uint32_t result = 0; 122 if (offset == 0x0) { 123 result = id << 24; 124 } else if (offset == 0x1) { 125 result = ((TableSize - 1) << 16) | APICVersion; 126 } else if (offset == 0x2) { 127 result = arbId << 24; 128 } else if (offset >= 0x10 && offset <= (0x10 + TableSize * 2)) { 129 int index = (offset - 0x10) / 2; 130 if (offset % 2) { 131 result = redirTable[index].topDW; 132 } else { 133 result = redirTable[index].bottomDW; 134 } 135 } else { 136 warn("Access to undefined I/O APIC register %#x.\n", offset); 137 } 138 DPRINTF(I82094AA, 139 "Read %#x from I/O APIC register %#x.\n", result, offset); 140 return result; 141} 142 143void 144X86ISA::I82094AA::signalInterrupt(int line) 145{ 146 DPRINTF(I82094AA, "Received interrupt %d.\n", line); 147 assert(line < TableSize); 148 RedirTableEntry entry = redirTable[line]; 149 if (entry.mask) { 150 DPRINTF(I82094AA, "Entry was masked.\n"); 151 return; 152 } else { 153 TriggerIntMessage message; 154 message.destination = entry.dest; 155 if (entry.deliveryMode == DeliveryMode::ExtInt) { 156 assert(extIntPic); 157 message.vector = extIntPic->getVector(); 158 } else { 159 message.vector = entry.vector; 160 } 161 message.deliveryMode = entry.deliveryMode; 162 message.destMode = entry.destMode; 163 message.level = entry.polarity; 164 message.trigger = entry.trigger;
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165
166 if (DeliveryMode::isReserved(entry.deliveryMode)) {
167 fatal("Tried to use reserved delivery mode "
168 "for IO APIC entry %d.\n", line);
169 } else if (DTRACE(I82094AA)) {
170 DPRINTF(I82094AA, "Delivery mode is: %s.\n",
171 DeliveryMode::names[entry.deliveryMode]);
172 DPRINTF(I82094AA, "Vector is %#x.\n", message.vector);
173 }
174
175 if (entry.destMode == 0) {
176 DPRINTF(I82094AA,
177 "Sending interrupt to APIC ID %d.\n", entry.dest);
178 PacketPtr pkt = buildIntRequest(entry.dest, message);
179 if (sys->getMemoryMode() == Enums::timing)
180 intPort->sendMessageTiming(pkt, latency);
181 else if (sys->getMemoryMode() == Enums::atomic)
182 intPort->sendMessageAtomic(pkt);
183 else
184 panic("Unrecognized memory mode.\n");
185 } else {
186 DPRINTF(I82094AA, "Sending interrupts to APIC IDs:"
187 "%s%s%s%s%s%s%s%s\n",
188 bits((int)entry.dest, 0) ? " 0": "",
189 bits((int)entry.dest, 1) ? " 1": "",
190 bits((int)entry.dest, 2) ? " 2": "",
191 bits((int)entry.dest, 3) ? " 3": "",
192 bits((int)entry.dest, 4) ? " 4": "",
193 bits((int)entry.dest, 5) ? " 5": "",
194 bits((int)entry.dest, 6) ? " 6": "",
195 bits((int)entry.dest, 7) ? " 7": ""
196 );
197 uint8_t dests = entry.dest;
198 uint8_t id = 0;
199 while(dests) {
200 if (dests & 0x1) {
201 PacketPtr pkt = buildIntRequest(id, message);
202 if (sys->getMemoryMode() == Enums::timing)
203 intPort->sendMessageTiming(pkt, latency);
204 else if (sys->getMemoryMode() == Enums::atomic)
205 intPort->sendMessageAtomic(pkt);
206 else
207 panic("Unrecognized memory mode.\n");
208 }
209 dests >>= 1;
210 id++;
211 }
212 }
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