1/* 2 * Copyright (c) 2008 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Gabe Black 29 */ 30 31#include "arch/x86/interrupts.hh" 32#include "arch/x86/intmessage.hh" 33#include "dev/x86/i82094aa.hh" 34#include "dev/x86/i8259.hh" 35#include "mem/packet.hh" 36#include "mem/packet_access.hh" 37#include "sim/system.hh" 38
| 1/* 2 * Copyright (c) 2008 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Gabe Black 29 */ 30 31#include "arch/x86/interrupts.hh" 32#include "arch/x86/intmessage.hh" 33#include "dev/x86/i82094aa.hh" 34#include "dev/x86/i8259.hh" 35#include "mem/packet.hh" 36#include "mem/packet_access.hh" 37#include "sim/system.hh" 38
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39X86ISA::I82094AA::I82094AA(Params *p) : PioDevice(p), IntDev(this),
| 39X86ISA::I82094AA::I82094AA(Params *p) : PioDevice(p), 40 IntDev(this, p->int_latency),
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40 latency(p->pio_latency), pioAddr(p->pio_addr), 41 extIntPic(p->external_int_pic), lowestPriorityOffset(0) 42{ 43 // This assumes there's only one I/O APIC in the system 44 initialApicId = id = p->apic_id; 45 assert(id <= 0xf); 46 arbId = id; 47 regSel = 0; 48 RedirTableEntry entry = 0; 49 entry.mask = 1; 50 for (int i = 0; i < TableSize; i++) { 51 redirTable[i] = entry; 52 pinStates[i] = false; 53 } 54} 55 56Tick 57X86ISA::I82094AA::read(PacketPtr pkt) 58{ 59 assert(pkt->getSize() == 4); 60 Addr offset = pkt->getAddr() - pioAddr; 61 switch(offset) { 62 case 0: 63 pkt->set<uint32_t>(regSel); 64 break; 65 case 16: 66 pkt->set<uint32_t>(readReg(regSel)); 67 break; 68 default: 69 panic("Illegal read from I/O APIC.\n"); 70 } 71 pkt->makeAtomicResponse(); 72 return latency; 73} 74 75Tick 76X86ISA::I82094AA::write(PacketPtr pkt) 77{ 78 assert(pkt->getSize() == 4); 79 Addr offset = pkt->getAddr() - pioAddr; 80 switch(offset) { 81 case 0: 82 regSel = pkt->get<uint32_t>(); 83 break; 84 case 16: 85 writeReg(regSel, pkt->get<uint32_t>()); 86 break; 87 default: 88 panic("Illegal write to I/O APIC.\n"); 89 } 90 pkt->makeAtomicResponse(); 91 return latency; 92} 93 94void 95X86ISA::I82094AA::writeReg(uint8_t offset, uint32_t value) 96{ 97 if (offset == 0x0) { 98 id = bits(value, 27, 24); 99 } else if (offset == 0x1) { 100 // The IOAPICVER register is read only. 101 } else if (offset == 0x2) { 102 arbId = bits(value, 27, 24); 103 } else if (offset >= 0x10 && offset <= (0x10 + TableSize * 2)) { 104 int index = (offset - 0x10) / 2; 105 if (offset % 2) { 106 redirTable[index].topDW = value; 107 redirTable[index].topReserved = 0; 108 } else { 109 redirTable[index].bottomDW = value; 110 redirTable[index].bottomReserved = 0; 111 } 112 } else { 113 warn("Access to undefined I/O APIC register %#x.\n", offset); 114 } 115 DPRINTF(I82094AA, 116 "Wrote %#x to I/O APIC register %#x .\n", value, offset); 117} 118 119uint32_t 120X86ISA::I82094AA::readReg(uint8_t offset) 121{ 122 uint32_t result = 0; 123 if (offset == 0x0) { 124 result = id << 24; 125 } else if (offset == 0x1) { 126 result = ((TableSize - 1) << 16) | APICVersion; 127 } else if (offset == 0x2) { 128 result = arbId << 24; 129 } else if (offset >= 0x10 && offset <= (0x10 + TableSize * 2)) { 130 int index = (offset - 0x10) / 2; 131 if (offset % 2) { 132 result = redirTable[index].topDW; 133 } else { 134 result = redirTable[index].bottomDW; 135 } 136 } else { 137 warn("Access to undefined I/O APIC register %#x.\n", offset); 138 } 139 DPRINTF(I82094AA, 140 "Read %#x from I/O APIC register %#x.\n", result, offset); 141 return result; 142} 143 144void 145X86ISA::I82094AA::signalInterrupt(int line) 146{ 147 DPRINTF(I82094AA, "Received interrupt %d.\n", line); 148 assert(line < TableSize); 149 RedirTableEntry entry = redirTable[line]; 150 if (entry.mask) { 151 DPRINTF(I82094AA, "Entry was masked.\n"); 152 return; 153 } else { 154 TriggerIntMessage message = 0; 155 message.destination = entry.dest; 156 if (entry.deliveryMode == DeliveryMode::ExtInt) { 157 assert(extIntPic); 158 message.vector = extIntPic->getVector(); 159 } else { 160 message.vector = entry.vector; 161 } 162 message.deliveryMode = entry.deliveryMode; 163 message.destMode = entry.destMode; 164 message.level = entry.polarity; 165 message.trigger = entry.trigger; 166 ApicList apics; 167 int numContexts = sys->numContexts(); 168 if (message.destMode == 0) { 169 if (message.deliveryMode == DeliveryMode::LowestPriority) { 170 panic("Lowest priority delivery mode from the " 171 "IO APIC aren't supported in physical " 172 "destination mode.\n"); 173 } 174 if (message.destination == 0xFF) { 175 for (int i = 0; i < numContexts; i++) { 176 apics.push_back(i); 177 } 178 } else { 179 apics.push_back(message.destination); 180 } 181 } else { 182 for (int i = 0; i < numContexts; i++) { 183 std::map<int, Interrupts *>::iterator localApicIt = 184 localApics.find(i); 185 assert(localApicIt != localApics.end()); 186 Interrupts *localApic = localApicIt->second; 187 if ((localApic->readReg(APIC_LOGICAL_DESTINATION) >> 24) & 188 message.destination) { 189 apics.push_back(localApicIt->first); 190 } 191 } 192 if (message.deliveryMode == DeliveryMode::LowestPriority && 193 apics.size()) { 194 // The manual seems to suggest that the chipset just does 195 // something reasonable for these instead of actually using 196 // state from the local APIC. We'll just rotate an offset 197 // through the set of APICs selected above. 198 uint64_t modOffset = lowestPriorityOffset % apics.size(); 199 lowestPriorityOffset++; 200 ApicList::iterator apicIt = apics.begin(); 201 while (modOffset--) { 202 apicIt++; 203 assert(apicIt != apics.end()); 204 } 205 int selected = *apicIt; 206 apics.clear(); 207 apics.push_back(selected); 208 } 209 } 210 intPort->sendMessage(apics, message, 211 sys->getMemoryMode() == Enums::timing); 212 } 213} 214 215void 216X86ISA::I82094AA::raiseInterruptPin(int number) 217{ 218 assert(number < TableSize); 219 if (!pinStates[number]) 220 signalInterrupt(number); 221 pinStates[number] = true; 222} 223 224void 225X86ISA::I82094AA::lowerInterruptPin(int number) 226{ 227 assert(number < TableSize); 228 pinStates[number] = false; 229} 230 231void 232X86ISA::I82094AA::registerLocalApic(int initialId, Interrupts *localApic) 233{ 234 assert(localApic); 235 localApics[initialId] = localApic; 236} 237 238X86ISA::I82094AA * 239I82094AAParams::create() 240{ 241 return new X86ISA::I82094AA(this); 242}
| 41 latency(p->pio_latency), pioAddr(p->pio_addr), 42 extIntPic(p->external_int_pic), lowestPriorityOffset(0) 43{ 44 // This assumes there's only one I/O APIC in the system 45 initialApicId = id = p->apic_id; 46 assert(id <= 0xf); 47 arbId = id; 48 regSel = 0; 49 RedirTableEntry entry = 0; 50 entry.mask = 1; 51 for (int i = 0; i < TableSize; i++) { 52 redirTable[i] = entry; 53 pinStates[i] = false; 54 } 55} 56 57Tick 58X86ISA::I82094AA::read(PacketPtr pkt) 59{ 60 assert(pkt->getSize() == 4); 61 Addr offset = pkt->getAddr() - pioAddr; 62 switch(offset) { 63 case 0: 64 pkt->set<uint32_t>(regSel); 65 break; 66 case 16: 67 pkt->set<uint32_t>(readReg(regSel)); 68 break; 69 default: 70 panic("Illegal read from I/O APIC.\n"); 71 } 72 pkt->makeAtomicResponse(); 73 return latency; 74} 75 76Tick 77X86ISA::I82094AA::write(PacketPtr pkt) 78{ 79 assert(pkt->getSize() == 4); 80 Addr offset = pkt->getAddr() - pioAddr; 81 switch(offset) { 82 case 0: 83 regSel = pkt->get<uint32_t>(); 84 break; 85 case 16: 86 writeReg(regSel, pkt->get<uint32_t>()); 87 break; 88 default: 89 panic("Illegal write to I/O APIC.\n"); 90 } 91 pkt->makeAtomicResponse(); 92 return latency; 93} 94 95void 96X86ISA::I82094AA::writeReg(uint8_t offset, uint32_t value) 97{ 98 if (offset == 0x0) { 99 id = bits(value, 27, 24); 100 } else if (offset == 0x1) { 101 // The IOAPICVER register is read only. 102 } else if (offset == 0x2) { 103 arbId = bits(value, 27, 24); 104 } else if (offset >= 0x10 && offset <= (0x10 + TableSize * 2)) { 105 int index = (offset - 0x10) / 2; 106 if (offset % 2) { 107 redirTable[index].topDW = value; 108 redirTable[index].topReserved = 0; 109 } else { 110 redirTable[index].bottomDW = value; 111 redirTable[index].bottomReserved = 0; 112 } 113 } else { 114 warn("Access to undefined I/O APIC register %#x.\n", offset); 115 } 116 DPRINTF(I82094AA, 117 "Wrote %#x to I/O APIC register %#x .\n", value, offset); 118} 119 120uint32_t 121X86ISA::I82094AA::readReg(uint8_t offset) 122{ 123 uint32_t result = 0; 124 if (offset == 0x0) { 125 result = id << 24; 126 } else if (offset == 0x1) { 127 result = ((TableSize - 1) << 16) | APICVersion; 128 } else if (offset == 0x2) { 129 result = arbId << 24; 130 } else if (offset >= 0x10 && offset <= (0x10 + TableSize * 2)) { 131 int index = (offset - 0x10) / 2; 132 if (offset % 2) { 133 result = redirTable[index].topDW; 134 } else { 135 result = redirTable[index].bottomDW; 136 } 137 } else { 138 warn("Access to undefined I/O APIC register %#x.\n", offset); 139 } 140 DPRINTF(I82094AA, 141 "Read %#x from I/O APIC register %#x.\n", result, offset); 142 return result; 143} 144 145void 146X86ISA::I82094AA::signalInterrupt(int line) 147{ 148 DPRINTF(I82094AA, "Received interrupt %d.\n", line); 149 assert(line < TableSize); 150 RedirTableEntry entry = redirTable[line]; 151 if (entry.mask) { 152 DPRINTF(I82094AA, "Entry was masked.\n"); 153 return; 154 } else { 155 TriggerIntMessage message = 0; 156 message.destination = entry.dest; 157 if (entry.deliveryMode == DeliveryMode::ExtInt) { 158 assert(extIntPic); 159 message.vector = extIntPic->getVector(); 160 } else { 161 message.vector = entry.vector; 162 } 163 message.deliveryMode = entry.deliveryMode; 164 message.destMode = entry.destMode; 165 message.level = entry.polarity; 166 message.trigger = entry.trigger; 167 ApicList apics; 168 int numContexts = sys->numContexts(); 169 if (message.destMode == 0) { 170 if (message.deliveryMode == DeliveryMode::LowestPriority) { 171 panic("Lowest priority delivery mode from the " 172 "IO APIC aren't supported in physical " 173 "destination mode.\n"); 174 } 175 if (message.destination == 0xFF) { 176 for (int i = 0; i < numContexts; i++) { 177 apics.push_back(i); 178 } 179 } else { 180 apics.push_back(message.destination); 181 } 182 } else { 183 for (int i = 0; i < numContexts; i++) { 184 std::map<int, Interrupts *>::iterator localApicIt = 185 localApics.find(i); 186 assert(localApicIt != localApics.end()); 187 Interrupts *localApic = localApicIt->second; 188 if ((localApic->readReg(APIC_LOGICAL_DESTINATION) >> 24) & 189 message.destination) { 190 apics.push_back(localApicIt->first); 191 } 192 } 193 if (message.deliveryMode == DeliveryMode::LowestPriority && 194 apics.size()) { 195 // The manual seems to suggest that the chipset just does 196 // something reasonable for these instead of actually using 197 // state from the local APIC. We'll just rotate an offset 198 // through the set of APICs selected above. 199 uint64_t modOffset = lowestPriorityOffset % apics.size(); 200 lowestPriorityOffset++; 201 ApicList::iterator apicIt = apics.begin(); 202 while (modOffset--) { 203 apicIt++; 204 assert(apicIt != apics.end()); 205 } 206 int selected = *apicIt; 207 apics.clear(); 208 apics.push_back(selected); 209 } 210 } 211 intPort->sendMessage(apics, message, 212 sys->getMemoryMode() == Enums::timing); 213 } 214} 215 216void 217X86ISA::I82094AA::raiseInterruptPin(int number) 218{ 219 assert(number < TableSize); 220 if (!pinStates[number]) 221 signalInterrupt(number); 222 pinStates[number] = true; 223} 224 225void 226X86ISA::I82094AA::lowerInterruptPin(int number) 227{ 228 assert(number < TableSize); 229 pinStates[number] = false; 230} 231 232void 233X86ISA::I82094AA::registerLocalApic(int initialId, Interrupts *localApic) 234{ 235 assert(localApic); 236 localApics[initialId] = localApic; 237} 238 239X86ISA::I82094AA * 240I82094AAParams::create() 241{ 242 return new X86ISA::I82094AA(this); 243}
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