1/*
2 * Copyright (c) 2008 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 */
30
31#include "arch/x86/interrupts.hh"
32#include "arch/x86/intmessage.hh"
33#include "cpu/base.hh"
34#include "debug/I82094AA.hh"
35#include "dev/x86/i82094aa.hh"
36#include "dev/x86/i8259.hh"
37#include "mem/packet.hh"
38#include "mem/packet_access.hh"
39#include "sim/system.hh"
40
41X86ISA::I82094AA::I82094AA(Params *p)
42 : BasicPioDevice(p, 20), IntDevice(this, p->int_latency),
43 extIntPic(p->external_int_pic), lowestPriorityOffset(0)
44{
45 // This assumes there's only one I/O APIC in the system and since the apic
46 // id is stored in a 8-bit field with 0xff meaning broadcast, the id must
47 // be less than 0xff
48
49 assert(p->apic_id < 0xff);
50 initialApicId = id = p->apic_id;
51 arbId = id;
52 regSel = 0;
53 RedirTableEntry entry = 0;
54 entry.mask = 1;
55 for (int i = 0; i < TableSize; i++) {
56 redirTable[i] = entry;
57 pinStates[i] = false;
58 }
59}
60
61void
62X86ISA::I82094AA::init()
63{
64 // The io apic must register its address ranges on both its pio port
65 // via the piodevice init() function and its int port that it inherited
66 // from IntDevice. Note IntDevice is not a SimObject itself.
67
68 BasicPioDevice::init();
69 IntDevice::init();
70}
71
72BaseMasterPort &
73X86ISA::I82094AA::getMasterPort(const std::string &if_name, PortID idx)
74{
75 if (if_name == "int_master")
76 return intMasterPort;
77 return BasicPioDevice::getMasterPort(if_name, idx);
78}
79
80AddrRangeList
81X86ISA::I82094AA::getIntAddrRange() const
82{
83 AddrRangeList ranges;
84 ranges.push_back(RangeEx(x86InterruptAddress(initialApicId, 0),
85 x86InterruptAddress(initialApicId, 0) +
86 PhysAddrAPICRangeSize));
87 return ranges;
88}
89
90Tick
| 1/*
2 * Copyright (c) 2008 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 */
30
31#include "arch/x86/interrupts.hh"
32#include "arch/x86/intmessage.hh"
33#include "cpu/base.hh"
34#include "debug/I82094AA.hh"
35#include "dev/x86/i82094aa.hh"
36#include "dev/x86/i8259.hh"
37#include "mem/packet.hh"
38#include "mem/packet_access.hh"
39#include "sim/system.hh"
40
41X86ISA::I82094AA::I82094AA(Params *p)
42 : BasicPioDevice(p, 20), IntDevice(this, p->int_latency),
43 extIntPic(p->external_int_pic), lowestPriorityOffset(0)
44{
45 // This assumes there's only one I/O APIC in the system and since the apic
46 // id is stored in a 8-bit field with 0xff meaning broadcast, the id must
47 // be less than 0xff
48
49 assert(p->apic_id < 0xff);
50 initialApicId = id = p->apic_id;
51 arbId = id;
52 regSel = 0;
53 RedirTableEntry entry = 0;
54 entry.mask = 1;
55 for (int i = 0; i < TableSize; i++) {
56 redirTable[i] = entry;
57 pinStates[i] = false;
58 }
59}
60
61void
62X86ISA::I82094AA::init()
63{
64 // The io apic must register its address ranges on both its pio port
65 // via the piodevice init() function and its int port that it inherited
66 // from IntDevice. Note IntDevice is not a SimObject itself.
67
68 BasicPioDevice::init();
69 IntDevice::init();
70}
71
72BaseMasterPort &
73X86ISA::I82094AA::getMasterPort(const std::string &if_name, PortID idx)
74{
75 if (if_name == "int_master")
76 return intMasterPort;
77 return BasicPioDevice::getMasterPort(if_name, idx);
78}
79
80AddrRangeList
81X86ISA::I82094AA::getIntAddrRange() const
82{
83 AddrRangeList ranges;
84 ranges.push_back(RangeEx(x86InterruptAddress(initialApicId, 0),
85 x86InterruptAddress(initialApicId, 0) +
86 PhysAddrAPICRangeSize));
87 return ranges;
88}
89
90Tick
|
91X86ISA::I82094AA::read(PacketPtr pkt)
92{
93 assert(pkt->getSize() == 4);
94 Addr offset = pkt->getAddr() - pioAddr;
95 switch(offset) {
96 case 0:
97 pkt->set<uint32_t>(regSel);
98 break;
99 case 16:
100 pkt->set<uint32_t>(readReg(regSel));
101 break;
102 default:
103 panic("Illegal read from I/O APIC.\n");
104 }
105 pkt->makeAtomicResponse();
106 return pioDelay;
107}
108
109Tick
110X86ISA::I82094AA::write(PacketPtr pkt)
111{
112 assert(pkt->getSize() == 4);
113 Addr offset = pkt->getAddr() - pioAddr;
114 switch(offset) {
115 case 0:
116 regSel = pkt->get<uint32_t>();
117 break;
118 case 16:
119 writeReg(regSel, pkt->get<uint32_t>());
120 break;
121 default:
122 panic("Illegal write to I/O APIC.\n");
123 }
124 pkt->makeAtomicResponse();
125 return pioDelay;
126}
127
128void
129X86ISA::I82094AA::writeReg(uint8_t offset, uint32_t value)
130{
131 if (offset == 0x0) {
132 id = bits(value, 31, 24);
133 } else if (offset == 0x1) {
134 // The IOAPICVER register is read only.
135 } else if (offset == 0x2) {
136 arbId = bits(value, 31, 24);
137 } else if (offset >= 0x10 && offset <= (0x10 + TableSize * 2)) {
138 int index = (offset - 0x10) / 2;
139 if (offset % 2) {
140 redirTable[index].topDW = value;
141 redirTable[index].topReserved = 0;
142 } else {
143 redirTable[index].bottomDW = value;
144 redirTable[index].bottomReserved = 0;
145 }
146 } else {
147 warn("Access to undefined I/O APIC register %#x.\n", offset);
148 }
149 DPRINTF(I82094AA,
150 "Wrote %#x to I/O APIC register %#x .\n", value, offset);
151}
152
153uint32_t
154X86ISA::I82094AA::readReg(uint8_t offset)
155{
156 uint32_t result = 0;
157 if (offset == 0x0) {
158 result = id << 24;
159 } else if (offset == 0x1) {
160 result = ((TableSize - 1) << 16) | APICVersion;
161 } else if (offset == 0x2) {
162 result = arbId << 24;
163 } else if (offset >= 0x10 && offset <= (0x10 + TableSize * 2)) {
164 int index = (offset - 0x10) / 2;
165 if (offset % 2) {
166 result = redirTable[index].topDW;
167 } else {
168 result = redirTable[index].bottomDW;
169 }
170 } else {
171 warn("Access to undefined I/O APIC register %#x.\n", offset);
172 }
173 DPRINTF(I82094AA,
174 "Read %#x from I/O APIC register %#x.\n", result, offset);
175 return result;
176}
177
178void
179X86ISA::I82094AA::signalInterrupt(int line)
180{
181 DPRINTF(I82094AA, "Received interrupt %d.\n", line);
182 assert(line < TableSize);
183 RedirTableEntry entry = redirTable[line];
184 if (entry.mask) {
185 DPRINTF(I82094AA, "Entry was masked.\n");
186 return;
187 } else {
188 TriggerIntMessage message = 0;
189 message.destination = entry.dest;
190 if (entry.deliveryMode == DeliveryMode::ExtInt) {
191 assert(extIntPic);
192 message.vector = extIntPic->getVector();
193 } else {
194 message.vector = entry.vector;
195 }
196 message.deliveryMode = entry.deliveryMode;
197 message.destMode = entry.destMode;
198 message.level = entry.polarity;
199 message.trigger = entry.trigger;
200 ApicList apics;
201 int numContexts = sys->numContexts();
202 if (message.destMode == 0) {
203 if (message.deliveryMode == DeliveryMode::LowestPriority) {
204 panic("Lowest priority delivery mode from the "
205 "IO APIC aren't supported in physical "
206 "destination mode.\n");
207 }
208 if (message.destination == 0xFF) {
209 for (int i = 0; i < numContexts; i++) {
210 apics.push_back(i);
211 }
212 } else {
213 apics.push_back(message.destination);
214 }
215 } else {
216 for (int i = 0; i < numContexts; i++) {
217 Interrupts *localApic = sys->getThreadContext(i)->
218 getCpuPtr()->getInterruptController();
219 if ((localApic->readReg(APIC_LOGICAL_DESTINATION) >> 24) &
220 message.destination) {
221 apics.push_back(localApic->getInitialApicId());
222 }
223 }
224 if (message.deliveryMode == DeliveryMode::LowestPriority &&
225 apics.size()) {
226 // The manual seems to suggest that the chipset just does
227 // something reasonable for these instead of actually using
228 // state from the local APIC. We'll just rotate an offset
229 // through the set of APICs selected above.
230 uint64_t modOffset = lowestPriorityOffset % apics.size();
231 lowestPriorityOffset++;
232 ApicList::iterator apicIt = apics.begin();
233 while (modOffset--) {
234 apicIt++;
235 assert(apicIt != apics.end());
236 }
237 int selected = *apicIt;
238 apics.clear();
239 apics.push_back(selected);
240 }
241 }
242 intMasterPort.sendMessage(apics, message, sys->isTimingMode());
243 }
244}
245
246void
247X86ISA::I82094AA::raiseInterruptPin(int number)
248{
249 assert(number < TableSize);
250 if (!pinStates[number])
251 signalInterrupt(number);
252 pinStates[number] = true;
253}
254
255void
256X86ISA::I82094AA::lowerInterruptPin(int number)
257{
258 assert(number < TableSize);
259 pinStates[number] = false;
260}
261
262void
263X86ISA::I82094AA::serialize(CheckpointOut &cp) const
264{
265 uint64_t* redirTableArray = (uint64_t*)redirTable;
266 SERIALIZE_SCALAR(regSel);
267 SERIALIZE_SCALAR(initialApicId);
268 SERIALIZE_SCALAR(id);
269 SERIALIZE_SCALAR(arbId);
270 SERIALIZE_SCALAR(lowestPriorityOffset);
271 SERIALIZE_ARRAY(redirTableArray, TableSize);
272 SERIALIZE_ARRAY(pinStates, TableSize);
273}
274
275void
276X86ISA::I82094AA::unserialize(CheckpointIn &cp)
277{
278 uint64_t redirTableArray[TableSize];
279 UNSERIALIZE_SCALAR(regSel);
280 UNSERIALIZE_SCALAR(initialApicId);
281 UNSERIALIZE_SCALAR(id);
282 UNSERIALIZE_SCALAR(arbId);
283 UNSERIALIZE_SCALAR(lowestPriorityOffset);
284 UNSERIALIZE_ARRAY(redirTableArray, TableSize);
285 UNSERIALIZE_ARRAY(pinStates, TableSize);
286 for (int i = 0; i < TableSize; i++) {
287 redirTable[i] = (RedirTableEntry)redirTableArray[i];
288 }
289}
290
291X86ISA::I82094AA *
292I82094AAParams::create()
293{
294 return new X86ISA::I82094AA(this);
295}
| 100X86ISA::I82094AA::read(PacketPtr pkt)
101{
102 assert(pkt->getSize() == 4);
103 Addr offset = pkt->getAddr() - pioAddr;
104 switch(offset) {
105 case 0:
106 pkt->set<uint32_t>(regSel);
107 break;
108 case 16:
109 pkt->set<uint32_t>(readReg(regSel));
110 break;
111 default:
112 panic("Illegal read from I/O APIC.\n");
113 }
114 pkt->makeAtomicResponse();
115 return pioDelay;
116}
117
118Tick
119X86ISA::I82094AA::write(PacketPtr pkt)
120{
121 assert(pkt->getSize() == 4);
122 Addr offset = pkt->getAddr() - pioAddr;
123 switch(offset) {
124 case 0:
125 regSel = pkt->get<uint32_t>();
126 break;
127 case 16:
128 writeReg(regSel, pkt->get<uint32_t>());
129 break;
130 default:
131 panic("Illegal write to I/O APIC.\n");
132 }
133 pkt->makeAtomicResponse();
134 return pioDelay;
135}
136
137void
138X86ISA::I82094AA::writeReg(uint8_t offset, uint32_t value)
139{
140 if (offset == 0x0) {
141 id = bits(value, 31, 24);
142 } else if (offset == 0x1) {
143 // The IOAPICVER register is read only.
144 } else if (offset == 0x2) {
145 arbId = bits(value, 31, 24);
146 } else if (offset >= 0x10 && offset <= (0x10 + TableSize * 2)) {
147 int index = (offset - 0x10) / 2;
148 if (offset % 2) {
149 redirTable[index].topDW = value;
150 redirTable[index].topReserved = 0;
151 } else {
152 redirTable[index].bottomDW = value;
153 redirTable[index].bottomReserved = 0;
154 }
155 } else {
156 warn("Access to undefined I/O APIC register %#x.\n", offset);
157 }
158 DPRINTF(I82094AA,
159 "Wrote %#x to I/O APIC register %#x .\n", value, offset);
160}
161
162uint32_t
163X86ISA::I82094AA::readReg(uint8_t offset)
164{
165 uint32_t result = 0;
166 if (offset == 0x0) {
167 result = id << 24;
168 } else if (offset == 0x1) {
169 result = ((TableSize - 1) << 16) | APICVersion;
170 } else if (offset == 0x2) {
171 result = arbId << 24;
172 } else if (offset >= 0x10 && offset <= (0x10 + TableSize * 2)) {
173 int index = (offset - 0x10) / 2;
174 if (offset % 2) {
175 result = redirTable[index].topDW;
176 } else {
177 result = redirTable[index].bottomDW;
178 }
179 } else {
180 warn("Access to undefined I/O APIC register %#x.\n", offset);
181 }
182 DPRINTF(I82094AA,
183 "Read %#x from I/O APIC register %#x.\n", result, offset);
184 return result;
185}
186
187void
188X86ISA::I82094AA::signalInterrupt(int line)
189{
190 DPRINTF(I82094AA, "Received interrupt %d.\n", line);
191 assert(line < TableSize);
192 RedirTableEntry entry = redirTable[line];
193 if (entry.mask) {
194 DPRINTF(I82094AA, "Entry was masked.\n");
195 return;
196 } else {
197 TriggerIntMessage message = 0;
198 message.destination = entry.dest;
199 if (entry.deliveryMode == DeliveryMode::ExtInt) {
200 assert(extIntPic);
201 message.vector = extIntPic->getVector();
202 } else {
203 message.vector = entry.vector;
204 }
205 message.deliveryMode = entry.deliveryMode;
206 message.destMode = entry.destMode;
207 message.level = entry.polarity;
208 message.trigger = entry.trigger;
209 ApicList apics;
210 int numContexts = sys->numContexts();
211 if (message.destMode == 0) {
212 if (message.deliveryMode == DeliveryMode::LowestPriority) {
213 panic("Lowest priority delivery mode from the "
214 "IO APIC aren't supported in physical "
215 "destination mode.\n");
216 }
217 if (message.destination == 0xFF) {
218 for (int i = 0; i < numContexts; i++) {
219 apics.push_back(i);
220 }
221 } else {
222 apics.push_back(message.destination);
223 }
224 } else {
225 for (int i = 0; i < numContexts; i++) {
226 Interrupts *localApic = sys->getThreadContext(i)->
227 getCpuPtr()->getInterruptController();
228 if ((localApic->readReg(APIC_LOGICAL_DESTINATION) >> 24) &
229 message.destination) {
230 apics.push_back(localApic->getInitialApicId());
231 }
232 }
233 if (message.deliveryMode == DeliveryMode::LowestPriority &&
234 apics.size()) {
235 // The manual seems to suggest that the chipset just does
236 // something reasonable for these instead of actually using
237 // state from the local APIC. We'll just rotate an offset
238 // through the set of APICs selected above.
239 uint64_t modOffset = lowestPriorityOffset % apics.size();
240 lowestPriorityOffset++;
241 ApicList::iterator apicIt = apics.begin();
242 while (modOffset--) {
243 apicIt++;
244 assert(apicIt != apics.end());
245 }
246 int selected = *apicIt;
247 apics.clear();
248 apics.push_back(selected);
249 }
250 }
251 intMasterPort.sendMessage(apics, message, sys->isTimingMode());
252 }
253}
254
255void
256X86ISA::I82094AA::raiseInterruptPin(int number)
257{
258 assert(number < TableSize);
259 if (!pinStates[number])
260 signalInterrupt(number);
261 pinStates[number] = true;
262}
263
264void
265X86ISA::I82094AA::lowerInterruptPin(int number)
266{
267 assert(number < TableSize);
268 pinStates[number] = false;
269}
270
271void
272X86ISA::I82094AA::serialize(CheckpointOut &cp) const
273{
274 uint64_t* redirTableArray = (uint64_t*)redirTable;
275 SERIALIZE_SCALAR(regSel);
276 SERIALIZE_SCALAR(initialApicId);
277 SERIALIZE_SCALAR(id);
278 SERIALIZE_SCALAR(arbId);
279 SERIALIZE_SCALAR(lowestPriorityOffset);
280 SERIALIZE_ARRAY(redirTableArray, TableSize);
281 SERIALIZE_ARRAY(pinStates, TableSize);
282}
283
284void
285X86ISA::I82094AA::unserialize(CheckpointIn &cp)
286{
287 uint64_t redirTableArray[TableSize];
288 UNSERIALIZE_SCALAR(regSel);
289 UNSERIALIZE_SCALAR(initialApicId);
290 UNSERIALIZE_SCALAR(id);
291 UNSERIALIZE_SCALAR(arbId);
292 UNSERIALIZE_SCALAR(lowestPriorityOffset);
293 UNSERIALIZE_ARRAY(redirTableArray, TableSize);
294 UNSERIALIZE_ARRAY(pinStates, TableSize);
295 for (int i = 0; i < TableSize; i++) {
296 redirTable[i] = (RedirTableEntry)redirTableArray[i];
297 }
298}
299
300X86ISA::I82094AA *
301I82094AAParams::create()
302{
303 return new X86ISA::I82094AA(this);
304}
|