1# Copyright (c) 2008 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright
9# notice, this list of conditions and the following disclaimer in the
10# documentation and/or other materials provided with the distribution;
11# neither the name of the copyright holders nor the names of its
12# contributors may be used to endorse or promote products derived from
13# this software without specific prior written permission.
14#
15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26#
27# Authors: Gabe Black
28
29from m5.params import *
30from m5.proxy import *
31from Cmos import Cmos
32from I8042 import I8042
33from I82094AA import I82094AA
34from I8237 import I8237
35from I8254 import I8254
36from I8259 import I8259
37from Ide import IdeController
38from PcSpeaker import PcSpeaker
39from X86IntPin import X86IntLine
40from m5.SimObject import SimObject
41
42def x86IOAddress(port):
43 IO_address_space_base = 0x8000000000000000
44 return IO_address_space_base + port;
45
46class SouthBridge(SimObject):
47 type = 'SouthBridge'
48 cxx_header = "dev/x86/south_bridge.hh"
49 platform = Param.Platform(Parent.any, "Platform this device is part of")
50
51 _pic1 = I8259(pio_addr=x86IOAddress(0x20), mode='I8259Master')
52 _pic2 = I8259(pio_addr=x86IOAddress(0xA0), mode='I8259Slave')
53 _cmos = Cmos(pio_addr=x86IOAddress(0x70))
54 _dma1 = I8237(pio_addr=x86IOAddress(0x0))
55 _keyboard = I8042(data_port=x86IOAddress(0x60), \
56 command_port=x86IOAddress(0x64))
57 _pit = I8254(pio_addr=x86IOAddress(0x40))
58 _speaker = PcSpeaker(pio_addr=x86IOAddress(0x61))
59 _io_apic = I82094AA(pio_addr=0xFEC00000)
60
61 pic1 = Param.I8259(_pic1, "Master PIC")
62 pic2 = Param.I8259(_pic2, "Slave PIC")
63 cmos = Param.Cmos(_cmos, "CMOS memory and real time clock device")
64 dma1 = Param.I8237(_dma1, "The first dma controller")
65 keyboard = Param.I8042(_keyboard, "The keyboard controller")
66 pit = Param.I8254(_pit, "Programmable interval timer")
67 speaker = Param.PcSpeaker(_speaker, "PC speaker")
68 io_apic = Param.I82094AA(_io_apic, "I/O APIC")
69
70 # IDE controller
71 ide = IdeController(disks=[], pci_func=0, pci_dev=4, pci_bus=0)
72 ide.BAR0 = 0x1f0
73 ide.BAR0LegacyIO = True
74 ide.BAR1 = 0x3f4
75 ide.BAR1Size = '3B'
76 ide.BAR1LegacyIO = True
77 ide.BAR2 = 0x170
78 ide.BAR2LegacyIO = True
79 ide.BAR3 = 0x374
80 ide.BAR3Size = '3B'
81 ide.BAR3LegacyIO = True
82 ide.BAR4 = 1
83 ide.Command = 0
84 ide.ProgIF = 0x80
85 ide.InterruptLine = 14
86 ide.InterruptPin = 1
| 1# Copyright (c) 2008 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright
9# notice, this list of conditions and the following disclaimer in the
10# documentation and/or other materials provided with the distribution;
11# neither the name of the copyright holders nor the names of its
12# contributors may be used to endorse or promote products derived from
13# this software without specific prior written permission.
14#
15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26#
27# Authors: Gabe Black
28
29from m5.params import *
30from m5.proxy import *
31from Cmos import Cmos
32from I8042 import I8042
33from I82094AA import I82094AA
34from I8237 import I8237
35from I8254 import I8254
36from I8259 import I8259
37from Ide import IdeController
38from PcSpeaker import PcSpeaker
39from X86IntPin import X86IntLine
40from m5.SimObject import SimObject
41
42def x86IOAddress(port):
43 IO_address_space_base = 0x8000000000000000
44 return IO_address_space_base + port;
45
46class SouthBridge(SimObject):
47 type = 'SouthBridge'
48 cxx_header = "dev/x86/south_bridge.hh"
49 platform = Param.Platform(Parent.any, "Platform this device is part of")
50
51 _pic1 = I8259(pio_addr=x86IOAddress(0x20), mode='I8259Master')
52 _pic2 = I8259(pio_addr=x86IOAddress(0xA0), mode='I8259Slave')
53 _cmos = Cmos(pio_addr=x86IOAddress(0x70))
54 _dma1 = I8237(pio_addr=x86IOAddress(0x0))
55 _keyboard = I8042(data_port=x86IOAddress(0x60), \
56 command_port=x86IOAddress(0x64))
57 _pit = I8254(pio_addr=x86IOAddress(0x40))
58 _speaker = PcSpeaker(pio_addr=x86IOAddress(0x61))
59 _io_apic = I82094AA(pio_addr=0xFEC00000)
60
61 pic1 = Param.I8259(_pic1, "Master PIC")
62 pic2 = Param.I8259(_pic2, "Slave PIC")
63 cmos = Param.Cmos(_cmos, "CMOS memory and real time clock device")
64 dma1 = Param.I8237(_dma1, "The first dma controller")
65 keyboard = Param.I8042(_keyboard, "The keyboard controller")
66 pit = Param.I8254(_pit, "Programmable interval timer")
67 speaker = Param.PcSpeaker(_speaker, "PC speaker")
68 io_apic = Param.I82094AA(_io_apic, "I/O APIC")
69
70 # IDE controller
71 ide = IdeController(disks=[], pci_func=0, pci_dev=4, pci_bus=0)
72 ide.BAR0 = 0x1f0
73 ide.BAR0LegacyIO = True
74 ide.BAR1 = 0x3f4
75 ide.BAR1Size = '3B'
76 ide.BAR1LegacyIO = True
77 ide.BAR2 = 0x170
78 ide.BAR2LegacyIO = True
79 ide.BAR3 = 0x374
80 ide.BAR3Size = '3B'
81 ide.BAR3LegacyIO = True
82 ide.BAR4 = 1
83 ide.Command = 0
84 ide.ProgIF = 0x80
85 ide.InterruptLine = 14
86 ide.InterruptPin = 1
|
87
88 def attachIO(self, bus, dma_ports):
89 # Route interupt signals
90 self.int_lines = \
91 [X86IntLine(source=self.pic1.output, sink=self.io_apic.pin(0)),
92 X86IntLine(source=self.pic2.output, sink=self.pic1.pin(2)),
93 X86IntLine(source=self.cmos.int_pin, sink=self.pic2.pin(0)),
94 X86IntLine(source=self.pit.int_pin, sink=self.pic1.pin(0)),
95 X86IntLine(source=self.pit.int_pin, sink=self.io_apic.pin(2)),
96 X86IntLine(source=self.keyboard.keyboard_int_pin,
97 sink=self.io_apic.pin(1)),
98 X86IntLine(source=self.keyboard.mouse_int_pin,
99 sink=self.io_apic.pin(12))]
100 # Tell the devices about each other
101 self.pic1.slave = self.pic2
102 self.speaker.i8254 = self.pit
103 self.io_apic.external_int_pic = self.pic1
104 # Connect to the bus
105 self.cmos.pio = bus.master
106 self.dma1.pio = bus.master
107 self.ide.pio = bus.master
108 self.ide.config = bus.master
109 if dma_ports.count(self.ide.dma) == 0:
110 self.ide.dma = bus.slave
111 self.keyboard.pio = bus.master
112 self.pic1.pio = bus.master
113 self.pic2.pio = bus.master
114 self.pit.pio = bus.master
115 self.speaker.pio = bus.master
116 self.io_apic.pio = bus.master
117 self.io_apic.int_master = bus.slave
| 88
89 def attachIO(self, bus, dma_ports):
90 # Route interupt signals
91 self.int_lines = \
92 [X86IntLine(source=self.pic1.output, sink=self.io_apic.pin(0)),
93 X86IntLine(source=self.pic2.output, sink=self.pic1.pin(2)),
94 X86IntLine(source=self.cmos.int_pin, sink=self.pic2.pin(0)),
95 X86IntLine(source=self.pit.int_pin, sink=self.pic1.pin(0)),
96 X86IntLine(source=self.pit.int_pin, sink=self.io_apic.pin(2)),
97 X86IntLine(source=self.keyboard.keyboard_int_pin,
98 sink=self.io_apic.pin(1)),
99 X86IntLine(source=self.keyboard.mouse_int_pin,
100 sink=self.io_apic.pin(12))]
101 # Tell the devices about each other
102 self.pic1.slave = self.pic2
103 self.speaker.i8254 = self.pit
104 self.io_apic.external_int_pic = self.pic1
105 # Connect to the bus
106 self.cmos.pio = bus.master
107 self.dma1.pio = bus.master
108 self.ide.pio = bus.master
109 self.ide.config = bus.master
110 if dma_ports.count(self.ide.dma) == 0:
111 self.ide.dma = bus.slave
112 self.keyboard.pio = bus.master
113 self.pic1.pio = bus.master
114 self.pic2.pio = bus.master
115 self.pit.pio = bus.master
116 self.speaker.pio = bus.master
117 self.io_apic.pio = bus.master
118 self.io_apic.int_master = bus.slave
|