Pc.py (8929:4148f9af0b70) Pc.py (9338:97b4a2be1e5b)
1# Copyright (c) 2008 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

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37from Uart import Uart8250
38
39def x86IOAddress(port):
40 IO_address_space_base = 0x8000000000000000
41 return IO_address_space_base + port;
42
43class Pc(Platform):
44 type = 'Pc'
1# Copyright (c) 2008 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

--- 28 unchanged lines hidden (view full) ---

37from Uart import Uart8250
38
39def x86IOAddress(port):
40 IO_address_space_base = 0x8000000000000000
41 return IO_address_space_base + port;
42
43class Pc(Platform):
44 type = 'Pc'
45 cxx_header = "dev/x86/pc.hh"
45 system = Param.System(Parent.any, "system")
46
47 pciconfig = PciConfigAll()
48
49 south_bridge = SouthBridge()
50
51 # "Non-existant" port used for timing purposes by the linux kernel
52 i_dont_exist = IsaFake(pio_addr=x86IOAddress(0x80), pio_size=1)

--- 30 unchanged lines hidden --- 		46 system = Param.System(Parent.any, "system")
47
48 pciconfig = PciConfigAll()
49
50 south_bridge = SouthBridge()
51
52 # "Non-existant" port used for timing purposes by the linux kernel
53 i_dont_exist = IsaFake(pio_addr=x86IOAddress(0x80), pio_size=1)

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