pci.cc (10602:3499de20ab3a) pci.cc (10672:e2716d523716)
1/*
2 * Copyright (c) 2014 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 109 unchanged lines hidden (view full) ---

118 DPRINTF(VIOPci, " DEVICE_STATUS request\n");
119 assert(size == sizeof(uint8_t));
120 pkt->set<uint8_t>(vio.getDeviceStatus());
121 break;
122
123 case OFF_ISR_STATUS: {
124 DPRINTF(VIOPci, " ISR_STATUS\n");
125 assert(size == sizeof(uint8_t));
1/*
2 * Copyright (c) 2014 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 109 unchanged lines hidden (view full) ---

118 DPRINTF(VIOPci, " DEVICE_STATUS request\n");
119 assert(size == sizeof(uint8_t));
120 pkt->set<uint8_t>(vio.getDeviceStatus());
121 break;
122
123 case OFF_ISR_STATUS: {
124 DPRINTF(VIOPci, " ISR_STATUS\n");
125 assert(size == sizeof(uint8_t));
126 uint8_t isr_status(interruptDeliveryPending ? 1 : 0);
127 interruptDeliveryPending = false;
126 const uint8_t isr_status(interruptDeliveryPending ? 1 : 0);
127 if (interruptDeliveryPending) {
128 interruptDeliveryPending = false;
129 intrClear();
130 }
128 pkt->set<uint8_t>(isr_status);
129 } break;
130
131 default:
132 panic("Unhandled read offset (0x%x)\n", offset);
133 }
134
135 return 0;

--- 87 unchanged lines hidden --- 		131 pkt->set<uint8_t>(isr_status);
132 } break;
133
134 default:
135 panic("Unhandled read offset (0x%x)\n", offset);
136 }
137
138 return 0;

--- 87 unchanged lines hidden ---