1/*
2 * Copyright (c) 2014 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Andreas Sandberg
38 */
39
40#include "dev/virtio/pci.hh"
41
42#include "debug/VIOIface.hh"
43#include "mem/packet_access.hh"
44#include "params/PciVirtIO.hh"
45
46PciVirtIO::PciVirtIO(const Params *params)
47 : PciDevice(params), queueNotify(0), interruptDeliveryPending(false),
48 vio(*params->vio), callbackKick(this)
49{
50 // Override the subsystem ID with the device ID from VirtIO
51 config.subsystemID = htole(vio.deviceId);
52 BARSize[0] = BAR0_SIZE_BASE + vio.configSize;
53
54 vio.registerKickCallback(&callbackKick);
55}
56
57PciVirtIO::~PciVirtIO()
58{
59}
60
61Tick
62PciVirtIO::read(PacketPtr pkt)
63{
64 const unsigned M5_VAR_USED size(pkt->getSize());
65 int bar;
66 Addr offset;
67 if (!getBAR(pkt->getAddr(), bar, offset))
68 panic("Invalid PCI memory access to unmapped memory.\n");
69 assert(bar == 0);
70
71 DPRINTF(VIOIface, "Reading offset 0x%x [len: %i]\n", offset, size);
72
73 // Forward device configuration writes to the device VirtIO model
74 if (offset >= OFF_VIO_DEVICE) {
75 vio.readConfig(pkt, offset - OFF_VIO_DEVICE);
76 return 0;
77 }
78
79 pkt->makeResponse();
80
81 switch(offset) {
82 case OFF_DEVICE_FEATURES:
83 DPRINTF(VIOIface, " DEVICE_FEATURES request\n");
84 assert(size == sizeof(uint32_t));
85 pkt->set<uint32_t>(vio.deviceFeatures);
86 break;
87
88 case OFF_GUEST_FEATURES:
89 DPRINTF(VIOIface, " GUEST_FEATURES request\n");
90 assert(size == sizeof(uint32_t));
91 pkt->set<uint32_t>(vio.getGuestFeatures());
92 break;
93
94 case OFF_QUEUE_ADDRESS:
95 DPRINTF(VIOIface, " QUEUE_ADDRESS request\n");
96 assert(size == sizeof(uint32_t));
97 pkt->set<uint32_t>(vio.getQueueAddress());
98 break;
99
100 case OFF_QUEUE_SIZE:
101 DPRINTF(VIOIface, " QUEUE_SIZE request\n");
102 assert(size == sizeof(uint16_t));
103 pkt->set<uint16_t>(vio.getQueueSize());
104 break;
105
106 case OFF_QUEUE_SELECT:
107 DPRINTF(VIOIface, " QUEUE_SELECT\n");
108 assert(size == sizeof(uint16_t));
109 pkt->set<uint16_t>(vio.getQueueSelect());
110 break;
111
112 case OFF_QUEUE_NOTIFY:
113 DPRINTF(VIOIface, " QUEUE_NOTIFY request\n");
114 assert(size == sizeof(uint16_t));
115 pkt->set<uint16_t>(queueNotify);
116 break;
117
118 case OFF_DEVICE_STATUS:
119 DPRINTF(VIOIface, " DEVICE_STATUS request\n");
120 assert(size == sizeof(uint8_t));
121 pkt->set<uint8_t>(vio.getDeviceStatus());
122 break;
123
124 case OFF_ISR_STATUS: {
125 DPRINTF(VIOIface, " ISR_STATUS\n");
126 assert(size == sizeof(uint8_t));
127 const uint8_t isr_status(interruptDeliveryPending ? 1 : 0);
128 if (interruptDeliveryPending) {
129 interruptDeliveryPending = false;
130 intrClear();
131 }
132 pkt->set<uint8_t>(isr_status);
133 } break;
134
135 default:
136 panic("Unhandled read offset (0x%x)\n", offset);
137 }
138
139 return 0;
140}
141
142Tick
143PciVirtIO::write(PacketPtr pkt)
144{
145 const unsigned M5_VAR_USED size(pkt->getSize());
146 int bar;
147 Addr offset;
148 if (!getBAR(pkt->getAddr(), bar, offset))
149 panic("Invalid PCI memory access to unmapped memory.\n");
150 assert(bar == 0);
151
152 DPRINTF(VIOIface, "Writing offset 0x%x [len: %i]\n", offset, size);
153
154 // Forward device configuration writes to the device VirtIO model
155 if (offset >= OFF_VIO_DEVICE) {
156 vio.writeConfig(pkt, offset - OFF_VIO_DEVICE);
157 return 0;
158 }
159
160 pkt->makeResponse();
161
162 switch(offset) {
163 case OFF_DEVICE_FEATURES:
164 warn("Guest tried to write device features.");
165 break;
166
167 case OFF_GUEST_FEATURES:
168 DPRINTF(VIOIface, " WRITE GUEST_FEATURES request\n");
169 assert(size == sizeof(uint32_t));
170 vio.setGuestFeatures(pkt->get<uint32_t>());
171 break;
172
173 case OFF_QUEUE_ADDRESS:
174 DPRINTF(VIOIface, " WRITE QUEUE_ADDRESS\n");
175 assert(size == sizeof(uint32_t));
176 vio.setQueueAddress(pkt->get<uint32_t>());
177 break;
178
179 case OFF_QUEUE_SIZE:
180 panic("Guest tried to write queue size.");
181 break;
182
183 case OFF_QUEUE_SELECT:
184 DPRINTF(VIOIface, " WRITE QUEUE_SELECT\n");
185 assert(size == sizeof(uint16_t));
186 vio.setQueueSelect(pkt->get<uint16_t>());
187 break;
188
189 case OFF_QUEUE_NOTIFY:
190 DPRINTF(VIOIface, " WRITE QUEUE_NOTIFY\n");
191 assert(size == sizeof(uint16_t));
192 queueNotify = pkt->get<uint16_t>();
193 vio.onNotify(queueNotify);
194 break;
195
196 case OFF_DEVICE_STATUS: {
197 assert(size == sizeof(uint8_t));
198 uint8_t status(pkt->get<uint8_t>());
199 DPRINTF(VIOIface, "VirtIO set status: 0x%x\n", status);
200 vio.setDeviceStatus(status);
201 } break;
202
203 case OFF_ISR_STATUS:
204 warn("Guest tried to write ISR status.");
205 break;
206
207 default:
208 panic("Unhandled read offset (0x%x)\n", offset);
209 }
210
211 return 0;
212}
213
214void
215PciVirtIO::kick()
216{
217 DPRINTF(VIOIface, "kick(): Sending interrupt...\n");
218 interruptDeliveryPending = true;
219 intrPost();
220}
221
222PciVirtIO *
223PciVirtIOParams::create()
224{
225 return new PciVirtIO(this);
226}