1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Ali Saidi
29 */
30
31/** @file
32 * This device implements the niagara I/O Bridge chip. The device manages
33 * internal (ipi) and external (serial, pci via jbus).
34 */
35
36#ifndef __DEV_SPARC_IOB_HH__
37#define __DEV_SPARC_IOB_HH__
38
39#include "dev/disk_image.hh"
40#include "dev/io_device.hh"
41#include "params/Iob.hh"
42
43class IntrControl;
44
45const int MaxNiagaraProcs = 32;
46// IOB Managment Addresses
47const Addr IntManAddr = 0x0000;
48const Addr IntManSize = 0x0020;
49const Addr IntCtlAddr = 0x0400;
50const Addr IntCtlSize = 0x0020;
51const Addr JIntVecAddr = 0x0A00;
52const Addr IntVecDisAddr = 0x0800;
53const Addr IntVecDisSize = 0x0100;
54
55
56// IOB Control Addresses
57const Addr JIntData0Addr = 0x0400;
58const Addr JIntData1Addr = 0x0500;
59const Addr JIntDataA0Addr = 0x0600;
60const Addr JIntDataA1Addr = 0x0700;
61const Addr JIntBusyAddr = 0x0900;
62const Addr JIntBusySize = 0x0100;
63const Addr JIntABusyAddr = 0x0B00;
64
65
66// IOB Masks
67const uint64_t IntManMask = 0x01F3F;
68const uint64_t IntCtlMask = 0x00006;
69const uint64_t JIntVecMask = 0x0003F;
70const uint64_t IntVecDis = 0x31F3F;
71const uint64_t JIntBusyMask = 0x0003F;
72
73
74class Iob : public PioDevice
75{
76 private:
77 IntrControl *ic;
78 Addr iobManAddr;
79 Addr iobManSize;
80 Addr iobJBusAddr;
81 Addr iobJBusSize;
82 Tick pioDelay;
83
84 enum DeviceId {
85 Interal = 0,
86 Error = 1,
87 SSI = 2,
88 Reserved = 3,
89 NumDeviceIds
90 };
91
92 struct IntMan {
93 int cpu;
94 int vector;
95 };
96
97 struct IntCtl {
98 bool mask;
99 bool pend;
100 };
101
102 struct IntBusy {
103 bool busy;
104 int source;
105 };
106
107 enum Type {
108 Interrupt,
109 Reset,
110 Idle,
111 Resume
112 };
113
114 IntMan intMan[NumDeviceIds];
115 IntCtl intCtl[NumDeviceIds];
116 uint64_t jIntVec;
117 uint64_t jBusData0[MaxNiagaraProcs];
118 uint64_t jBusData1[MaxNiagaraProcs];
119 IntBusy jIntBusy[MaxNiagaraProcs];
120
121 void writeIob(PacketPtr pkt);
122 void writeJBus(PacketPtr pkt);
123 void readIob(PacketPtr pkt);
124 void readJBus(PacketPtr pkt);
125
126 public:
127 typedef IobParams Params;
128 Iob(const Params *p);
129
130 const Params *
131 params() const
132 {
133 return dynamic_cast<const Params *>(_params);
134 }
135
136 virtual Tick read(PacketPtr pkt);
137 virtual Tick write(PacketPtr pkt);
138 void generateIpi(Type type, int cpu_id, int vector);
139 void receiveDeviceInterrupt(DeviceId devid);
140 bool receiveJBusInterrupt(int cpu_id, int source, uint64_t d0,
141 uint64_t d1);
142
143 AddrRangeList getAddrRanges() const;
144
| 1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Ali Saidi
29 */
30
31/** @file
32 * This device implements the niagara I/O Bridge chip. The device manages
33 * internal (ipi) and external (serial, pci via jbus).
34 */
35
36#ifndef __DEV_SPARC_IOB_HH__
37#define __DEV_SPARC_IOB_HH__
38
39#include "dev/disk_image.hh"
40#include "dev/io_device.hh"
41#include "params/Iob.hh"
42
43class IntrControl;
44
45const int MaxNiagaraProcs = 32;
46// IOB Managment Addresses
47const Addr IntManAddr = 0x0000;
48const Addr IntManSize = 0x0020;
49const Addr IntCtlAddr = 0x0400;
50const Addr IntCtlSize = 0x0020;
51const Addr JIntVecAddr = 0x0A00;
52const Addr IntVecDisAddr = 0x0800;
53const Addr IntVecDisSize = 0x0100;
54
55
56// IOB Control Addresses
57const Addr JIntData0Addr = 0x0400;
58const Addr JIntData1Addr = 0x0500;
59const Addr JIntDataA0Addr = 0x0600;
60const Addr JIntDataA1Addr = 0x0700;
61const Addr JIntBusyAddr = 0x0900;
62const Addr JIntBusySize = 0x0100;
63const Addr JIntABusyAddr = 0x0B00;
64
65
66// IOB Masks
67const uint64_t IntManMask = 0x01F3F;
68const uint64_t IntCtlMask = 0x00006;
69const uint64_t JIntVecMask = 0x0003F;
70const uint64_t IntVecDis = 0x31F3F;
71const uint64_t JIntBusyMask = 0x0003F;
72
73
74class Iob : public PioDevice
75{
76 private:
77 IntrControl *ic;
78 Addr iobManAddr;
79 Addr iobManSize;
80 Addr iobJBusAddr;
81 Addr iobJBusSize;
82 Tick pioDelay;
83
84 enum DeviceId {
85 Interal = 0,
86 Error = 1,
87 SSI = 2,
88 Reserved = 3,
89 NumDeviceIds
90 };
91
92 struct IntMan {
93 int cpu;
94 int vector;
95 };
96
97 struct IntCtl {
98 bool mask;
99 bool pend;
100 };
101
102 struct IntBusy {
103 bool busy;
104 int source;
105 };
106
107 enum Type {
108 Interrupt,
109 Reset,
110 Idle,
111 Resume
112 };
113
114 IntMan intMan[NumDeviceIds];
115 IntCtl intCtl[NumDeviceIds];
116 uint64_t jIntVec;
117 uint64_t jBusData0[MaxNiagaraProcs];
118 uint64_t jBusData1[MaxNiagaraProcs];
119 IntBusy jIntBusy[MaxNiagaraProcs];
120
121 void writeIob(PacketPtr pkt);
122 void writeJBus(PacketPtr pkt);
123 void readIob(PacketPtr pkt);
124 void readJBus(PacketPtr pkt);
125
126 public:
127 typedef IobParams Params;
128 Iob(const Params *p);
129
130 const Params *
131 params() const
132 {
133 return dynamic_cast<const Params *>(_params);
134 }
135
136 virtual Tick read(PacketPtr pkt);
137 virtual Tick write(PacketPtr pkt);
138 void generateIpi(Type type, int cpu_id, int vector);
139 void receiveDeviceInterrupt(DeviceId devid);
140 bool receiveJBusInterrupt(int cpu_id, int source, uint64_t d0,
141 uint64_t d1);
142
143 AddrRangeList getAddrRanges() const;
144
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