1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Ali Saidi
29 */
30
31/** @file
32 * This device implements the niagara I/O Bridge chip. The device manages
33 * internal (ipi) and external (serial, pci via jbus).
34 */
35
36#ifndef __DEV_SPARC_IOB_HH__
37#define __DEV_SPARC_IOB_HH__
38
39#include "base/range.hh"
| 1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Ali Saidi
29 */
30
31/** @file
32 * This device implements the niagara I/O Bridge chip. The device manages
33 * internal (ipi) and external (serial, pci via jbus).
34 */
35
36#ifndef __DEV_SPARC_IOB_HH__
37#define __DEV_SPARC_IOB_HH__
38
39#include "base/range.hh"
|
42#include "params/Iob.hh"
43
44class IntrControl;
45
46const int MaxNiagaraProcs = 32;
47// IOB Managment Addresses
48const Addr IntManAddr = 0x0000;
49const Addr IntManSize = 0x0020;
50const Addr IntCtlAddr = 0x0400;
51const Addr IntCtlSize = 0x0020;
52const Addr JIntVecAddr = 0x0A00;
53const Addr IntVecDisAddr = 0x0800;
54const Addr IntVecDisSize = 0x0100;
55
56
57// IOB Control Addresses
58const Addr JIntData0Addr = 0x0400;
59const Addr JIntData1Addr = 0x0500;
60const Addr JIntDataA0Addr = 0x0600;
61const Addr JIntDataA1Addr = 0x0700;
62const Addr JIntBusyAddr = 0x0900;
63const Addr JIntBusySize = 0x0100;
64const Addr JIntABusyAddr = 0x0B00;
65
66
67// IOB Masks
68const uint64_t IntManMask = 0x01F3F;
69const uint64_t IntCtlMask = 0x00006;
70const uint64_t JIntVecMask = 0x0003F;
71const uint64_t IntVecDis = 0x31F3F;
72const uint64_t JIntBusyMask = 0x0003F;
73
74
75class Iob : public PioDevice
76{
77 private:
78 IntrControl *ic;
79 Addr iobManAddr;
80 Addr iobManSize;
81 Addr iobJBusAddr;
82 Addr iobJBusSize;
83 Tick pioDelay;
84
85 enum DeviceId {
86 Interal = 0,
87 Error = 1,
88 SSI = 2,
89 Reserved = 3,
90 NumDeviceIds
91 };
92
93 struct IntMan {
94 int cpu;
95 int vector;
96 };
97
98 struct IntCtl {
99 bool mask;
100 bool pend;
101 };
102
103 struct IntBusy {
104 bool busy;
105 int source;
106 };
107
108 enum Type {
109 Interrupt,
110 Reset,
111 Idle,
112 Resume
113 };
114
115 IntMan intMan[NumDeviceIds];
116 IntCtl intCtl[NumDeviceIds];
117 uint64_t jIntVec;
118 uint64_t jBusData0[MaxNiagaraProcs];
119 uint64_t jBusData1[MaxNiagaraProcs];
120 IntBusy jIntBusy[MaxNiagaraProcs];
121
122 void writeIob(PacketPtr pkt);
123 void writeJBus(PacketPtr pkt);
124 void readIob(PacketPtr pkt);
125 void readJBus(PacketPtr pkt);
126
127 public:
128 typedef IobParams Params;
129 Iob(const Params *p);
130
131 const Params *
132 params() const
133 {
134 return dynamic_cast<const Params *>(_params);
135 }
136
137 virtual Tick read(PacketPtr pkt);
138 virtual Tick write(PacketPtr pkt);
139 void generateIpi(Type type, int cpu_id, int vector);
140 void receiveDeviceInterrupt(DeviceId devid);
141 bool receiveJBusInterrupt(int cpu_id, int source, uint64_t d0,
142 uint64_t d1);
143
144 void addressRanges(AddrRangeList &range_list);
145
146 virtual void serialize(std::ostream &os);
147 virtual void unserialize(Checkpoint *cp, const std::string §ion);
148
149};
150
151#endif //__DEV_SPARC_IOB_HH__
152
| 42#include "params/Iob.hh"
43
44class IntrControl;
45
46const int MaxNiagaraProcs = 32;
47// IOB Managment Addresses
48const Addr IntManAddr = 0x0000;
49const Addr IntManSize = 0x0020;
50const Addr IntCtlAddr = 0x0400;
51const Addr IntCtlSize = 0x0020;
52const Addr JIntVecAddr = 0x0A00;
53const Addr IntVecDisAddr = 0x0800;
54const Addr IntVecDisSize = 0x0100;
55
56
57// IOB Control Addresses
58const Addr JIntData0Addr = 0x0400;
59const Addr JIntData1Addr = 0x0500;
60const Addr JIntDataA0Addr = 0x0600;
61const Addr JIntDataA1Addr = 0x0700;
62const Addr JIntBusyAddr = 0x0900;
63const Addr JIntBusySize = 0x0100;
64const Addr JIntABusyAddr = 0x0B00;
65
66
67// IOB Masks
68const uint64_t IntManMask = 0x01F3F;
69const uint64_t IntCtlMask = 0x00006;
70const uint64_t JIntVecMask = 0x0003F;
71const uint64_t IntVecDis = 0x31F3F;
72const uint64_t JIntBusyMask = 0x0003F;
73
74
75class Iob : public PioDevice
76{
77 private:
78 IntrControl *ic;
79 Addr iobManAddr;
80 Addr iobManSize;
81 Addr iobJBusAddr;
82 Addr iobJBusSize;
83 Tick pioDelay;
84
85 enum DeviceId {
86 Interal = 0,
87 Error = 1,
88 SSI = 2,
89 Reserved = 3,
90 NumDeviceIds
91 };
92
93 struct IntMan {
94 int cpu;
95 int vector;
96 };
97
98 struct IntCtl {
99 bool mask;
100 bool pend;
101 };
102
103 struct IntBusy {
104 bool busy;
105 int source;
106 };
107
108 enum Type {
109 Interrupt,
110 Reset,
111 Idle,
112 Resume
113 };
114
115 IntMan intMan[NumDeviceIds];
116 IntCtl intCtl[NumDeviceIds];
117 uint64_t jIntVec;
118 uint64_t jBusData0[MaxNiagaraProcs];
119 uint64_t jBusData1[MaxNiagaraProcs];
120 IntBusy jIntBusy[MaxNiagaraProcs];
121
122 void writeIob(PacketPtr pkt);
123 void writeJBus(PacketPtr pkt);
124 void readIob(PacketPtr pkt);
125 void readJBus(PacketPtr pkt);
126
127 public:
128 typedef IobParams Params;
129 Iob(const Params *p);
130
131 const Params *
132 params() const
133 {
134 return dynamic_cast<const Params *>(_params);
135 }
136
137 virtual Tick read(PacketPtr pkt);
138 virtual Tick write(PacketPtr pkt);
139 void generateIpi(Type type, int cpu_id, int vector);
140 void receiveDeviceInterrupt(DeviceId devid);
141 bool receiveJBusInterrupt(int cpu_id, int source, uint64_t d0,
142 uint64_t d1);
143
144 void addressRanges(AddrRangeList &range_list);
145
146 virtual void serialize(std::ostream &os);
147 virtual void unserialize(Checkpoint *cp, const std::string §ion);
148
149};
150
151#endif //__DEV_SPARC_IOB_HH__
152
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