iob.cc (8711:c7e14f52c682) iob.cc (8739:925f15f96322)
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 28 unchanged lines hidden (view full) ---

37
38#include <cstring>
39
40#include "arch/sparc/faults.hh"
41#include "arch/sparc/isa_traits.hh"
42#include "base/bitfield.hh"
43#include "base/trace.hh"
44#include "cpu/intr_control.hh"
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 28 unchanged lines hidden (view full) ---

37
38#include <cstring>
39
40#include "arch/sparc/faults.hh"
41#include "arch/sparc/isa_traits.hh"
42#include "base/bitfield.hh"
43#include "base/trace.hh"
44#include "cpu/intr_control.hh"
45#include "cpu/thread_context.hh"
45#include "debug/Iob.hh"
46#include "dev/sparc/iob.hh"
47#include "dev/platform.hh"
48#include "mem/packet_access.hh"
49#include "mem/port.hh"
50#include "sim/faults.hh"
51#include "sim/system.hh"
52

--- 267 unchanged lines hidden (view full) ---

320 jIntBusy[cpu_id].source = source;
321 jBusData0[cpu_id] = d0;
322 jBusData1[cpu_id] = d1;
323
324 ic->post(cpu_id, SparcISA::IT_INT_VEC, jIntVec);
325 return true;
326}
327
46#include "debug/Iob.hh"
47#include "dev/sparc/iob.hh"
48#include "dev/platform.hh"
49#include "mem/packet_access.hh"
50#include "mem/port.hh"
51#include "sim/faults.hh"
52#include "sim/system.hh"
53

--- 267 unchanged lines hidden (view full) ---

321 jIntBusy[cpu_id].source = source;
322 jBusData0[cpu_id] = d0;
323 jBusData1[cpu_id] = d1;
324
325 ic->post(cpu_id, SparcISA::IT_INT_VEC, jIntVec);
326 return true;
327}
328
328AddrRangeList
329Iob::getAddrRanges()
329void
330Iob::addressRanges(AddrRangeList &range_list)
330{
331{
331 AddrRangeList ranges;
332 ranges.push_back(RangeSize(iobManAddr, iobManSize));
333 ranges.push_back(RangeSize(iobJBusAddr, iobJBusSize));
334 return ranges;
332 range_list.clear();
333 range_list.push_back(RangeSize(iobManAddr, iobManSize));
334 range_list.push_back(RangeSize(iobJBusAddr, iobJBusSize));
335}
336
337
338void
339Iob::serialize(std::ostream &os)
340{
341
342 SERIALIZE_SCALAR(jIntVec);

--- 39 unchanged lines hidden --- 		335}
336
337
338void
339Iob::serialize(std::ostream &os)
340{
341
342 SERIALIZE_SCALAR(jIntVec);

--- 39 unchanged lines hidden ---