iob.cc (4762:c94e103c83ad) | iob.cc (4870:fcc39d001154) |
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1/* 2 * Copyright (c) 2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 31 unchanged lines hidden (view full) --- 40#include "arch/sparc/isa_traits.hh" 41#include "arch/sparc/faults.hh" 42#include "base/trace.hh" 43#include "cpu/intr_control.hh" 44#include "dev/sparc/iob.hh" 45#include "dev/platform.hh" 46#include "mem/port.hh" 47#include "mem/packet_access.hh" | 1/* 2 * Copyright (c) 2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 31 unchanged lines hidden (view full) --- 40#include "arch/sparc/isa_traits.hh" 41#include "arch/sparc/faults.hh" 42#include "base/trace.hh" 43#include "cpu/intr_control.hh" 44#include "dev/sparc/iob.hh" 45#include "dev/platform.hh" 46#include "mem/port.hh" 47#include "mem/packet_access.hh" |
48#include "sim/builder.hh" |
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48#include "sim/faults.hh" 49#include "sim/system.hh" 50 | 49#include "sim/faults.hh" 50#include "sim/system.hh" 51 |
51Iob::Iob(const Params *p) | 52Iob::Iob(Params *p) |
52 : PioDevice(p), ic(p->platform->intrctrl) 53{ 54 iobManAddr = ULL(0x9800000000); 55 iobManSize = ULL(0x0100000000); 56 iobJBusAddr = ULL(0x9F00000000); 57 iobJBusSize = ULL(0x0100000000); 58 assert (params()->system->threadContexts.size() <= MaxNiagaraProcs); 59 // Get the interrupt controller from the platform --- 6 unchanged lines hidden (view full) --- 66 intCtl[x].pend = false; 67 } 68 69} 70 71Tick 72Iob::read(PacketPtr pkt) 73{ | 53 : PioDevice(p), ic(p->platform->intrctrl) 54{ 55 iobManAddr = ULL(0x9800000000); 56 iobManSize = ULL(0x0100000000); 57 iobJBusAddr = ULL(0x9F00000000); 58 iobJBusSize = ULL(0x0100000000); 59 assert (params()->system->threadContexts.size() <= MaxNiagaraProcs); 60 // Get the interrupt controller from the platform --- 6 unchanged lines hidden (view full) --- 67 intCtl[x].pend = false; 68 } 69 70} 71 72Tick 73Iob::read(PacketPtr pkt) 74{ |
74 assert(pkt->result == Packet::Unknown); | |
75 76 if (pkt->getAddr() >= iobManAddr && pkt->getAddr() < iobManAddr + iobManSize) 77 readIob(pkt); 78 else if (pkt->getAddr() >= iobJBusAddr && pkt->getAddr() < iobJBusAddr+iobJBusSize) 79 readJBus(pkt); 80 else 81 panic("Invalid address reached Iob\n"); 82 | 75 76 if (pkt->getAddr() >= iobManAddr && pkt->getAddr() < iobManAddr + iobManSize) 77 readIob(pkt); 78 else if (pkt->getAddr() >= iobJBusAddr && pkt->getAddr() < iobJBusAddr+iobJBusSize) 79 readJBus(pkt); 80 else 81 panic("Invalid address reached Iob\n"); 82 |
83 pkt->result = Packet::Success; | 83 pkt->makeAtomicResponse(); |
84 return pioDelay; 85} 86 87void 88Iob::readIob(PacketPtr pkt) 89{ 90 Addr accessAddr = pkt->getAddr() - iobManAddr; 91 int index; --- 78 unchanged lines hidden (view full) --- 170 if (pkt->getAddr() >= iobManAddr && pkt->getAddr() < iobManAddr + iobManSize) 171 writeIob(pkt); 172 else if (pkt->getAddr() >= iobJBusAddr && pkt->getAddr() < iobJBusAddr+iobJBusSize) 173 writeJBus(pkt); 174 else 175 panic("Invalid address reached Iob\n"); 176 177 | 84 return pioDelay; 85} 86 87void 88Iob::readIob(PacketPtr pkt) 89{ 90 Addr accessAddr = pkt->getAddr() - iobManAddr; 91 int index; --- 78 unchanged lines hidden (view full) --- 170 if (pkt->getAddr() >= iobManAddr && pkt->getAddr() < iobManAddr + iobManSize) 171 writeIob(pkt); 172 else if (pkt->getAddr() >= iobJBusAddr && pkt->getAddr() < iobJBusAddr+iobJBusSize) 173 writeJBus(pkt); 174 else 175 panic("Invalid address reached Iob\n"); 176 177 |
178 pkt->result = Packet::Success; | 178 pkt->makeAtomicResponse(); |
179 return pioDelay; 180} 181 182void 183Iob::writeIob(PacketPtr pkt) 184{ 185 Addr accessAddr = pkt->getAddr() - iobManAddr; 186 int index; --- 179 unchanged lines hidden (view full) --- 366 paramIn(cp, csprintf("%s.Int%d", name(), x), "pend", intCtl[x].pend); 367 }; 368 for (int x = 0; x < MaxNiagaraProcs; x++) { 369 paramIn(cp, csprintf("%s.jIntBusy%d", name(), x), "busy", jIntBusy[x].busy); 370 paramIn(cp, csprintf("%s.jIntBusy%d", name(), x), "source", jIntBusy[x].source); 371 }; 372} 373 | 179 return pioDelay; 180} 181 182void 183Iob::writeIob(PacketPtr pkt) 184{ 185 Addr accessAddr = pkt->getAddr() - iobManAddr; 186 int index; --- 179 unchanged lines hidden (view full) --- 366 paramIn(cp, csprintf("%s.Int%d", name(), x), "pend", intCtl[x].pend); 367 }; 368 for (int x = 0; x < MaxNiagaraProcs; x++) { 369 paramIn(cp, csprintf("%s.jIntBusy%d", name(), x), "busy", jIntBusy[x].busy); 370 paramIn(cp, csprintf("%s.jIntBusy%d", name(), x), "source", jIntBusy[x].source); 371 }; 372} 373 |
374Iob * 375IobParams::create() | 374 375 376 377BEGIN_DECLARE_SIM_OBJECT_PARAMS(Iob) 378 Param<Tick> pio_latency; 379 SimObjectParam<Platform *> platform; 380 SimObjectParam<System *> system; 381END_DECLARE_SIM_OBJECT_PARAMS(Iob) 382 383BEGIN_INIT_SIM_OBJECT_PARAMS(Iob) 384 385 INIT_PARAM(pio_latency, "Programmed IO latency"), 386 INIT_PARAM(platform, "platform"), 387 INIT_PARAM(system, "system object") 388 389END_INIT_SIM_OBJECT_PARAMS(Iob) 390 391CREATE_SIM_OBJECT(Iob) |
376{ | 392{ |
377 return new Iob(this); | 393 Iob::Params *p = new Iob::Params; 394 p->name = getInstanceName(); 395 p->pio_delay = pio_latency; 396 p->platform = platform; 397 p->system = system; 398 return new Iob(p); |
378} | 399} |
400 401REGISTER_SIM_OBJECT("Iob", Iob) |
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