iob.cc (4130:a611c874376e) iob.cc (4194:af4f6022394b)
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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33 * interrupts and posts them to the CPU when needed. It holds mask registers and
34 * various status registers for CPUs to check what interrupts are pending as
35 * well as facilities to send IPIs to other cpus.
36 */
37
38#include <cstring>
39
40#include "arch/sparc/isa_traits.hh"
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 24 unchanged lines hidden (view full) ---

33 * interrupts and posts them to the CPU when needed. It holds mask registers and
34 * various status registers for CPUs to check what interrupts are pending as
35 * well as facilities to send IPIs to other cpus.
36 */
37
38#include <cstring>
39
40#include "arch/sparc/isa_traits.hh"
41#include "arch/sparc/faults.hh"
41#include "base/trace.hh"
42#include "cpu/intr_control.hh"
43#include "dev/sparc/iob.hh"
44#include "dev/platform.hh"
45#include "mem/port.hh"
46#include "mem/packet_access.hh"
47#include "sim/builder.hh"
42#include "base/trace.hh"
43#include "cpu/intr_control.hh"
44#include "dev/sparc/iob.hh"
45#include "dev/platform.hh"
46#include "mem/port.hh"
47#include "mem/packet_access.hh"
48#include "sim/builder.hh"
49#include "sim/faults.hh"
48#include "sim/system.hh"
49
50Iob::Iob(Params *p)
51 : PioDevice(p), ic(p->platform->intrctrl)
52{
53 iobManAddr = ULL(0x9800000000);
54 iobManSize = ULL(0x0100000000);
55 iobJBusAddr = ULL(0x9F00000000);

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256 intCtl[devid].pend = true;
257 ic->post(intMan[devid].cpu, SparcISA::IT_INT_VEC, intMan[devid].vector);
258}
259
260
261void
262Iob::generateIpi(Type type, int cpu_id, int vector)
263{
50#include "sim/system.hh"
51
52Iob::Iob(Params *p)
53 : PioDevice(p), ic(p->platform->intrctrl)
54{
55 iobManAddr = ULL(0x9800000000);
56 iobManSize = ULL(0x0100000000);
57 iobJBusAddr = ULL(0x9F00000000);

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258 intCtl[devid].pend = true;
259 ic->post(intMan[devid].cpu, SparcISA::IT_INT_VEC, intMan[devid].vector);
260}
261
262
263void
264Iob::generateIpi(Type type, int cpu_id, int vector)
265{
264 // Only handle interrupts for the moment... Cpu Idle/reset/resume will be
265 // later
266 if (type != 0)
266 SparcISA::SparcFault<SparcISA::PowerOnReset> *por = new SparcISA::PowerOnReset();
267 if (cpu_id >= sys->getNumCPUs())
267 return;
268
268 return;
269
269 assert(type == 0);
270 ic->post(cpu_id, SparcISA::IT_INT_VEC, vector);
270 switch (type) {
271 case 0: // interrupt
272 ic->post(cpu_id, SparcISA::IT_INT_VEC, vector);
273 break;
274 case 1: // reset
275 warn("Sending reset to CPU: %d\n", cpu_id);
276 if (vector != por->trapType())
277 panic("Don't know how to set non-POR reset to cpu\n");
278 por->invoke(sys->threadContexts[cpu_id]);
279 sys->threadContexts[cpu_id]->activate();
280 break;
281 case 2: // idle -- this means stop executing and don't wake on interrupts
282 sys->threadContexts[cpu_id]->halt();
283 break;
284 case 3: // resume
285 sys->threadContexts[cpu_id]->activate();
286 break;
287 default:
288 panic("Invalid type to generate ipi\n");
289 }
271}
272
273bool
274Iob::receiveJBusInterrupt(int cpu_id, int source, uint64_t d0, uint64_t d1)
275{
276 // If we are already dealing with an interrupt for that cpu we can't deal
277 // with another one right now... come back later
278 if (jIntBusy[cpu_id].busy)

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291
292bool
293Iob::receiveJBusInterrupt(int cpu_id, int source, uint64_t d0, uint64_t d1)
294{
295 // If we are already dealing with an interrupt for that cpu we can't deal
296 // with another one right now... come back later
297 if (jIntBusy[cpu_id].busy)

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