iob.cc (4104:10b99ef0a7ff) iob.cc (4130:a611c874376e)
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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258}
259
260
261void
262Iob::generateIpi(Type type, int cpu_id, int vector)
263{
264 // Only handle interrupts for the moment... Cpu Idle/reset/resume will be
265 // later
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 249 unchanged lines hidden (view full) ---

258}
259
260
261void
262Iob::generateIpi(Type type, int cpu_id, int vector)
263{
264 // Only handle interrupts for the moment... Cpu Idle/reset/resume will be
265 // later
266 if (type != 0) {
267 warn("Ignoring IntVecDis write\n");
266 if (type != 0)
268 return;
267 return;
269 }
268
270 assert(type == 0);
271 ic->post(cpu_id, SparcISA::IT_INT_VEC, vector);
272}
273
274bool
275Iob::receiveJBusInterrupt(int cpu_id, int source, uint64_t d0, uint64_t d1)
276{
277 // If we are already dealing with an interrupt for that cpu we can't deal

--- 89 unchanged lines hidden --- 		269 assert(type == 0);
270 ic->post(cpu_id, SparcISA::IT_INT_VEC, vector);
271}
272
273bool
274Iob::receiveJBusInterrupt(int cpu_id, int source, uint64_t d0, uint64_t d1)
275{
276 // If we are already dealing with an interrupt for that cpu we can't deal

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