iob.cc (11793:ef606668d247) iob.cc (13231:c6c133f9e007)
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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91Iob::readIob(PacketPtr pkt)
92{
93 Addr accessAddr = pkt->getAddr() - iobManAddr;
94
95 assert(IntManAddr == 0);
96 if (accessAddr < IntManAddr + IntManSize) {
97 int index = (accessAddr - IntManAddr) >> 3;
98 uint64_t data = intMan[index].cpu << 8 | intMan[index].vector << 0;
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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91Iob::readIob(PacketPtr pkt)
92{
93 Addr accessAddr = pkt->getAddr() - iobManAddr;
94
95 assert(IntManAddr == 0);
96 if (accessAddr < IntManAddr + IntManSize) {
97 int index = (accessAddr - IntManAddr) >> 3;
98 uint64_t data = intMan[index].cpu << 8 | intMan[index].vector << 0;
99 pkt->set(data);
99 pkt->setBE(data);
100 return;
101 }
102
103 if (accessAddr >= IntCtlAddr && accessAddr < IntCtlAddr + IntCtlSize) {
104 int index = (accessAddr - IntCtlAddr) >> 3;
105 uint64_t data = intCtl[index].mask ? 1 << 2 : 0 |
106 intCtl[index].pend ? 1 << 0 : 0;
100 return;
101 }
102
103 if (accessAddr >= IntCtlAddr && accessAddr < IntCtlAddr + IntCtlSize) {
104 int index = (accessAddr - IntCtlAddr) >> 3;
105 uint64_t data = intCtl[index].mask ? 1 << 2 : 0 |
106 intCtl[index].pend ? 1 << 0 : 0;
107 pkt->set(data);
107 pkt->setBE(data);
108 return;
109 }
110
111 if (accessAddr == JIntVecAddr) {
108 return;
109 }
110
111 if (accessAddr == JIntVecAddr) {
112 pkt->set(jIntVec);
112 pkt->setBE(jIntVec);
113 return;
114 }
115
116 panic("Read to unknown IOB offset 0x%x\n", accessAddr);
117}
118
119void
120Iob::readJBus(PacketPtr pkt)
121{
122 Addr accessAddr = pkt->getAddr() - iobJBusAddr;
123 ContextID cpuid = pkt->req->contextId();
124 int index;
125 uint64_t data;
126
127
128
129
130 if (accessAddr >= JIntData0Addr && accessAddr < JIntData1Addr) {
131 index = (accessAddr - JIntData0Addr) >> 3;
113 return;
114 }
115
116 panic("Read to unknown IOB offset 0x%x\n", accessAddr);
117}
118
119void
120Iob::readJBus(PacketPtr pkt)
121{
122 Addr accessAddr = pkt->getAddr() - iobJBusAddr;
123 ContextID cpuid = pkt->req->contextId();
124 int index;
125 uint64_t data;
126
127
128
129
130 if (accessAddr >= JIntData0Addr && accessAddr < JIntData1Addr) {
131 index = (accessAddr - JIntData0Addr) >> 3;
132 pkt->set(jBusData0[index]);
132 pkt->setBE(jBusData0[index]);
133 return;
134 }
135
136 if (accessAddr >= JIntData1Addr && accessAddr < JIntDataA0Addr) {
137 index = (accessAddr - JIntData1Addr) >> 3;
133 return;
134 }
135
136 if (accessAddr >= JIntData1Addr && accessAddr < JIntDataA0Addr) {
137 index = (accessAddr - JIntData1Addr) >> 3;
138 pkt->set(jBusData1[index]);
138 pkt->setBE(jBusData1[index]);
139 return;
140 }
141
142 if (accessAddr == JIntDataA0Addr) {
139 return;
140 }
141
142 if (accessAddr == JIntDataA0Addr) {
143 pkt->set(jBusData0[cpuid]);
143 pkt->setBE(jBusData0[cpuid]);
144 return;
145 }
146
147 if (accessAddr == JIntDataA1Addr) {
144 return;
145 }
146
147 if (accessAddr == JIntDataA1Addr) {
148 pkt->set(jBusData1[cpuid]);
148 pkt->setBE(jBusData1[cpuid]);
149 return;
150 }
151
152 if (accessAddr >= JIntBusyAddr && accessAddr < JIntBusyAddr + JIntBusySize) {
153 index = (accessAddr - JIntBusyAddr) >> 3;
154 data = jIntBusy[index].busy ? 1 << 5 : 0 |
155 jIntBusy[index].source;
149 return;
150 }
151
152 if (accessAddr >= JIntBusyAddr && accessAddr < JIntBusyAddr + JIntBusySize) {
153 index = (accessAddr - JIntBusyAddr) >> 3;
154 data = jIntBusy[index].busy ? 1 << 5 : 0 |
155 jIntBusy[index].source;
156 pkt->set(data);
156 pkt->setBE(data);
157 return;
158 }
159 if (accessAddr == JIntABusyAddr) {
160 data = jIntBusy[cpuid].busy ? 1 << 5 : 0 |
161 jIntBusy[cpuid].source;
157 return;
158 }
159 if (accessAddr == JIntABusyAddr) {
160 data = jIntBusy[cpuid].busy ? 1 << 5 : 0 |
161 jIntBusy[cpuid].source;
162 pkt->set(data);
162 pkt->setBE(data);
163 return;
164 };
165
166 panic("Read to unknown JBus offset 0x%x\n", accessAddr);
167}
168
169Tick
170Iob::write(PacketPtr pkt)

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186{
187 Addr accessAddr = pkt->getAddr() - iobManAddr;
188 int index;
189 uint64_t data;
190
191 assert(IntManAddr == 0);
192 if (accessAddr < IntManAddr + IntManSize) {
193 index = (accessAddr - IntManAddr) >> 3;
163 return;
164 };
165
166 panic("Read to unknown JBus offset 0x%x\n", accessAddr);
167}
168
169Tick
170Iob::write(PacketPtr pkt)

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186{
187 Addr accessAddr = pkt->getAddr() - iobManAddr;
188 int index;
189 uint64_t data;
190
191 assert(IntManAddr == 0);
192 if (accessAddr < IntManAddr + IntManSize) {
193 index = (accessAddr - IntManAddr) >> 3;
194 data = pkt->get();
194 data = pkt->getBE<uint64_t>();
195 intMan[index].cpu = bits(data,12,8);
196 intMan[index].vector = bits(data,5,0);
197 DPRINTF(Iob, "Wrote IntMan %d cpu %d, vec %d\n", index,
198 intMan[index].cpu, intMan[index].vector);
199 return;
200 }
201
202 if (accessAddr >= IntCtlAddr && accessAddr < IntCtlAddr + IntCtlSize) {
203 index = (accessAddr - IntCtlAddr) >> 3;
195 intMan[index].cpu = bits(data,12,8);
196 intMan[index].vector = bits(data,5,0);
197 DPRINTF(Iob, "Wrote IntMan %d cpu %d, vec %d\n", index,
198 intMan[index].cpu, intMan[index].vector);
199 return;
200 }
201
202 if (accessAddr >= IntCtlAddr && accessAddr < IntCtlAddr + IntCtlSize) {
203 index = (accessAddr - IntCtlAddr) >> 3;
204 data = pkt->get();
204 data = pkt->getBE<uint64_t>();
205 intCtl[index].mask = bits(data,2,2);
206 if (bits(data,1,1))
207 intCtl[index].pend = false;
208 DPRINTF(Iob, "Wrote IntCtl %d pend %d cleared %d\n", index,
209 intCtl[index].pend, bits(data,2,2));
210 return;
211 }
212
213 if (accessAddr == JIntVecAddr) {
205 intCtl[index].mask = bits(data,2,2);
206 if (bits(data,1,1))
207 intCtl[index].pend = false;
208 DPRINTF(Iob, "Wrote IntCtl %d pend %d cleared %d\n", index,
209 intCtl[index].pend, bits(data,2,2));
210 return;
211 }
212
213 if (accessAddr == JIntVecAddr) {
214 jIntVec = bits(pkt->get(), 5,0);
214 jIntVec = bits(pkt->getBE<uint64_t>(), 5,0);
215 DPRINTF(Iob, "Wrote jIntVec %d\n", jIntVec);
216 return;
217 }
218
219 if (accessAddr >= IntVecDisAddr && accessAddr < IntVecDisAddr + IntVecDisSize) {
220 Type type;
221 int cpu_id;
222 int vector;
223 index = (accessAddr - IntManAddr) >> 3;
215 DPRINTF(Iob, "Wrote jIntVec %d\n", jIntVec);
216 return;
217 }
218
219 if (accessAddr >= IntVecDisAddr && accessAddr < IntVecDisAddr + IntVecDisSize) {
220 Type type;
221 int cpu_id;
222 int vector;
223 index = (accessAddr - IntManAddr) >> 3;
224 data = pkt->get();
224 data = pkt->getBE<uint64_t>();
225 type = (Type)bits(data,17,16);
226 cpu_id = bits(data, 12,8);
227 vector = bits(data,5,0);
228 generateIpi(type,cpu_id, vector);
229 return;
230 }
231
232 panic("Write to unknown IOB offset 0x%x\n", accessAddr);

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237{
238 Addr accessAddr = pkt->getAddr() - iobJBusAddr;
239 ContextID cpuid = pkt->req->contextId();
240 int index;
241 uint64_t data;
242
243 if (accessAddr >= JIntBusyAddr && accessAddr < JIntBusyAddr + JIntBusySize) {
244 index = (accessAddr - JIntBusyAddr) >> 3;
225 type = (Type)bits(data,17,16);
226 cpu_id = bits(data, 12,8);
227 vector = bits(data,5,0);
228 generateIpi(type,cpu_id, vector);
229 return;
230 }
231
232 panic("Write to unknown IOB offset 0x%x\n", accessAddr);

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237{
238 Addr accessAddr = pkt->getAddr() - iobJBusAddr;
239 ContextID cpuid = pkt->req->contextId();
240 int index;
241 uint64_t data;
242
243 if (accessAddr >= JIntBusyAddr && accessAddr < JIntBusyAddr + JIntBusySize) {
244 index = (accessAddr - JIntBusyAddr) >> 3;
245 data = pkt->get();
245 data = pkt->getBE<uint64_t>();
246 jIntBusy[index].busy = bits(data,5,5);
247 DPRINTF(Iob, "Wrote jIntBusy index %d busy: %d\n", index,
248 jIntBusy[index].busy);
249 return;
250 }
251 if (accessAddr == JIntABusyAddr) {
246 jIntBusy[index].busy = bits(data,5,5);
247 DPRINTF(Iob, "Wrote jIntBusy index %d busy: %d\n", index,
248 jIntBusy[index].busy);
249 return;
250 }
251 if (accessAddr == JIntABusyAddr) {
252 data = pkt->get();
252 data = pkt->getBE<uint64_t>();
253 jIntBusy[cpuid].busy = bits(data,5,5);
254 DPRINTF(Iob, "Wrote jIntBusy index %d busy: %d\n", cpuid,
255 jIntBusy[cpuid].busy);
256 return;
257 };
258
259 panic("Write to unknown JBus offset 0x%x\n", accessAddr);
260}

--- 124 unchanged lines hidden --- 		253 jIntBusy[cpuid].busy = bits(data,5,5);
254 DPRINTF(Iob, "Wrote jIntBusy index %d busy: %d\n", cpuid,
255 jIntBusy[cpuid].busy);
256 return;
257 };
258
259 panic("Write to unknown JBus offset 0x%x\n", accessAddr);
260}

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