1/* 2 * Copyright (c) 2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 249 unchanged lines hidden (view full) --- 258} 259 260 261void 262Iob::generateIpi(Type type, int cpu_id, int vector) 263{ 264 // Only handle interrupts for the moment... Cpu Idle/reset/resume will be 265 // later |
266 if (type != 0) |
267 return; |
268 |
269 assert(type == 0); 270 ic->post(cpu_id, SparcISA::IT_INT_VEC, vector); 271} 272 273bool 274Iob::receiveJBusInterrupt(int cpu_id, int source, uint64_t d0, uint64_t d1) 275{ 276 // If we are already dealing with an interrupt for that cpu we can't deal --- 89 unchanged lines hidden --- |