1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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187 int index;
188 uint64_t data;
189
190 if (accessAddr >= IntManAddr && accessAddr < IntManAddr + IntManSize) {
191 index = (accessAddr - IntManAddr) >> 3;
192 data = pkt->get<uint64_t>();
193 intMan[index].cpu = bits(data,12,8);
194 intMan[index].vector = bits(data,5,0);
195 return;
196 }
197
198 if (accessAddr >= IntCtlAddr && accessAddr < IntCtlAddr + IntCtlSize) {
199 index = (accessAddr - IntManAddr) >> 3;
200 data = pkt->get<uint64_t>();
201 intCtl[index].mask = bits(data,2,2);
202 if (bits(data,1,1))
203 intCtl[index].pend = false;
204 return;
205 }
206
207 if (accessAddr == JIntVecAddr) {
208 jIntVec = bits(pkt->get<uint64_t>(), 5,0);
209 return;
210 }
211
212 if (accessAddr >= IntVecDisAddr && accessAddr < IntVecDisAddr + IntVecDisSize) {
213 Type type;
214 int cpu_id;
215 int vector;
216 index = (accessAddr - IntManAddr) >> 3;

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232 int cpuid = pkt->req->getCpuNum();
233 int index;
234 uint64_t data;
235
236 if (accessAddr >= JIntBusyAddr && accessAddr < JIntBusyAddr + JIntBusySize) {
237 index = (accessAddr - JIntBusyAddr) >> 3;
238 data = pkt->get<uint64_t>();
239 jIntBusy[index].busy = bits(data,5,5);
240 return;
241 }
242 if (accessAddr == JIntABusyAddr) {
243 data = pkt->get<uint64_t>();
244 jIntBusy[cpuid].busy = bits(data,5,5);
245 return;
246 };
247
248 panic("Write to unknown JBus offset 0x%x\n", accessAddr);
249}
250
251void
252Iob::receiveDeviceInterrupt(DeviceId devid)
253{
254 assert(devid < NumDeviceIds);
255 if (intCtl[devid].mask)
256 return;
257 intCtl[devid].mask = true;
258 intCtl[devid].pend = true;
259 ic->post(intMan[devid].cpu, SparcISA::IT_INT_VEC, intMan[devid].vector);
260}
261
262
263void
264Iob::generateIpi(Type type, int cpu_id, int vector)
265{
266 SparcISA::SparcFault<SparcISA::PowerOnReset> *por = new SparcISA::PowerOnReset();
267 if (cpu_id >= sys->getNumCPUs())
268 return;
269
270 switch (type) {
271 case 0: // interrupt
272 ic->post(cpu_id, SparcISA::IT_INT_VEC, vector);
273 break;
274 case 1: // reset
275 warn("Sending reset to CPU: %d\n", cpu_id);
276 if (vector != por->trapType())
277 panic("Don't know how to set non-POR reset to cpu\n");
278 por->invoke(sys->threadContexts[cpu_id]);
279 sys->threadContexts[cpu_id]->activate();
280 break;
281 case 2: // idle -- this means stop executing and don't wake on interrupts
282 sys->threadContexts[cpu_id]->halt();
283 break;
284 case 3: // resume
285 sys->threadContexts[cpu_id]->activate();
286 break;
287 default:
288 panic("Invalid type to generate ipi\n");
289 }
290}
291
292bool
293Iob::receiveJBusInterrupt(int cpu_id, int source, uint64_t d0, uint64_t d1)
294{
295 // If we are already dealing with an interrupt for that cpu we can't deal
296 // with another one right now... come back later
297 if (jIntBusy[cpu_id].busy)
298 return false;
299
300 jIntBusy[cpu_id].busy = true;
301 jIntBusy[cpu_id].source = source;
302 jBusData0[cpu_id] = d0;
303 jBusData1[cpu_id] = d1;
304
305 ic->post(cpu_id, SparcISA::IT_INT_VEC, jIntVec);
306 return true;
307}

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