1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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33 * interrupts and posts them to the CPU when needed. It holds mask registers and
34 * various status registers for CPUs to check what interrupts are pending as
35 * well as facilities to send IPIs to other cpus.
36 */
37
38#include <cstring>
39
40#include "arch/sparc/isa_traits.hh"
41#include "base/trace.hh"
42#include "cpu/intr_control.hh"
43#include "dev/sparc/iob.hh"
44#include "dev/platform.hh"
45#include "mem/port.hh"
46#include "mem/packet_access.hh"
47#include "sim/builder.hh"
48#include "sim/system.hh"
49
50Iob::Iob(Params *p)
51 : PioDevice(p), ic(p->platform->intrctrl)
52{
53 iobManAddr = ULL(0x9800000000);
54 iobManSize = ULL(0x0100000000);
55 iobJBusAddr = ULL(0x9F00000000);

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256 intCtl[devid].pend = true;
257 ic->post(intMan[devid].cpu, SparcISA::IT_INT_VEC, intMan[devid].vector);
258}
259
260
261void
262Iob::generateIpi(Type type, int cpu_id, int vector)
263{
264 // Only handle interrupts for the moment... Cpu Idle/reset/resume will be
265 // later
266 if (type != 0)
267 return;
268
269 assert(type == 0);
270 ic->post(cpu_id, SparcISA::IT_INT_VEC, vector);
271}
272
273bool
274Iob::receiveJBusInterrupt(int cpu_id, int source, uint64_t d0, uint64_t d1)
275{
276 // If we are already dealing with an interrupt for that cpu we can't deal
277 // with another one right now... come back later
278 if (jIntBusy[cpu_id].busy)

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