1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Ali Saidi
29 */
30
31/** @file
32 * Time of date device implementation
33 */
34#include <sys/time.h>
35
36#include <deque>
37#include <string>
38#include <vector>
39
40#include "base/trace.hh"
41#include "dev/sparc/dtod.hh"
42#include "dev/platform.hh"
43#include "mem/packet_access.hh"
44#include "mem/port.hh"
45#include "sim/builder.hh"
46#include "sim/system.hh"
47
48using namespace std;
49using namespace TheISA;
50
51DumbTOD::DumbTOD(Params *p)
| 1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Ali Saidi
29 */
30
31/** @file
32 * Time of date device implementation
33 */
34#include <sys/time.h>
35
36#include <deque>
37#include <string>
38#include <vector>
39
40#include "base/trace.hh"
41#include "dev/sparc/dtod.hh"
42#include "dev/platform.hh"
43#include "mem/packet_access.hh"
44#include "mem/port.hh"
45#include "sim/builder.hh"
46#include "sim/system.hh"
47
48using namespace std;
49using namespace TheISA;
50
51DumbTOD::DumbTOD(Params *p)
|
52 : BasicPioDevice(p), todTime(p->init_time)
| 52 : BasicPioDevice(p)
|
53{
54 pioSize = 0x08;
55
56 struct tm tm;
| 53{
54 pioSize = 0x08;
55
56 struct tm tm;
|
57 gmtime_r((time_t*)&todTime, &tm);
| 57 parseTime(p->init_time, &tm);
58 todTime = timegm(&tm);
59
|
58 DPRINTFN("Real-time clock set to %s\n", asctime(&tm));
59 DPRINTFN("Real-time clock set to %d\n", todTime);
60}
61
62Tick
63DumbTOD::read(PacketPtr pkt)
64{
65 assert(pkt->result == Packet::Unknown);
66 assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
67 assert(pkt->getSize() == 8);
68
69 pkt->allocate();
70 pkt->set(todTime);
71 todTime += 1000;
72
73 pkt->result = Packet::Success;
74 return pioDelay;
75}
76
77Tick
78DumbTOD::write(PacketPtr pkt)
79{
80 panic("Dumb tod device doesn't support writes\n");
81}
82
83BEGIN_DECLARE_SIM_OBJECT_PARAMS(DumbTOD)
84
85 Param<Addr> pio_addr;
86 Param<Tick> pio_latency;
87 SimObjectParam<Platform *> platform;
88 SimObjectParam<System *> system;
| 60 DPRINTFN("Real-time clock set to %s\n", asctime(&tm));
61 DPRINTFN("Real-time clock set to %d\n", todTime);
62}
63
64Tick
65DumbTOD::read(PacketPtr pkt)
66{
67 assert(pkt->result == Packet::Unknown);
68 assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
69 assert(pkt->getSize() == 8);
70
71 pkt->allocate();
72 pkt->set(todTime);
73 todTime += 1000;
74
75 pkt->result = Packet::Success;
76 return pioDelay;
77}
78
79Tick
80DumbTOD::write(PacketPtr pkt)
81{
82 panic("Dumb tod device doesn't support writes\n");
83}
84
85BEGIN_DECLARE_SIM_OBJECT_PARAMS(DumbTOD)
86
87 Param<Addr> pio_addr;
88 Param<Tick> pio_latency;
89 SimObjectParam<Platform *> platform;
90 SimObjectParam<System *> system;
|
89 Param<time_t> time;
| 91 VectorParam<int> time;
|
90
91END_DECLARE_SIM_OBJECT_PARAMS(DumbTOD)
92
93BEGIN_INIT_SIM_OBJECT_PARAMS(DumbTOD)
94
95 INIT_PARAM(pio_addr, "Device Address"),
96 INIT_PARAM(pio_latency, "Programmed IO latency"),
97 INIT_PARAM(platform, "platform"),
98 INIT_PARAM(system, "system object"),
| 92
93END_DECLARE_SIM_OBJECT_PARAMS(DumbTOD)
94
95BEGIN_INIT_SIM_OBJECT_PARAMS(DumbTOD)
96
97 INIT_PARAM(pio_addr, "Device Address"),
98 INIT_PARAM(pio_latency, "Programmed IO latency"),
99 INIT_PARAM(platform, "platform"),
100 INIT_PARAM(system, "system object"),
|
99 INIT_PARAM(time, "System time to use (0 for actual time")
| 101 INIT_PARAM(time, "")
|
100
101END_INIT_SIM_OBJECT_PARAMS(DumbTOD)
102
103CREATE_SIM_OBJECT(DumbTOD)
104{
105 DumbTOD::Params *p = new DumbTOD::Params;
106 p->name =getInstanceName();
107 p->pio_addr = pio_addr;
108 p->pio_delay = pio_latency;
109 p->platform = platform;
110 p->system = system;
111 p->init_time = time;
112 return new DumbTOD(p);
113}
114
115REGISTER_SIM_OBJECT("DumbTOD", DumbTOD)
| 102
103END_INIT_SIM_OBJECT_PARAMS(DumbTOD)
104
105CREATE_SIM_OBJECT(DumbTOD)
106{
107 DumbTOD::Params *p = new DumbTOD::Params;
108 p->name =getInstanceName();
109 p->pio_addr = pio_addr;
110 p->pio_delay = pio_latency;
111 p->platform = platform;
112 p->system = system;
113 p->init_time = time;
114 return new DumbTOD(p);
115}
116
117REGISTER_SIM_OBJECT("DumbTOD", DumbTOD)
|