copy_engine.cc (12392:e0dbdf30a2a5) copy_engine.cc (13342:1ddb43f47325)
1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 179 unchanged lines hidden (view full) ---

188 ///
189 /// Handle read of register here
190 ///
191
192 if (daddr < 0x80) {
193 switch (daddr) {
194 case GEN_CHANCOUNT:
195 assert(size == sizeof(regs.chanCount));
1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 179 unchanged lines hidden (view full) ---

188 ///
189 /// Handle read of register here
190 ///
191
192 if (daddr < 0x80) {
193 switch (daddr) {
194 case GEN_CHANCOUNT:
195 assert(size == sizeof(regs.chanCount));
196 pkt->set(regs.chanCount);
196 pkt->setLE<uint8_t>(regs.chanCount);
197 break;
198 case GEN_XFERCAP:
199 assert(size == sizeof(regs.xferCap));
197 break;
198 case GEN_XFERCAP:
199 assert(size == sizeof(regs.xferCap));
200 pkt->set(regs.xferCap);
200 pkt->setLE<uint8_t>(regs.xferCap);
201 break;
202 case GEN_INTRCTRL:
203 assert(size == sizeof(uint8_t));
201 break;
202 case GEN_INTRCTRL:
203 assert(size == sizeof(uint8_t));
204 pkt->set(regs.intrctrl());
204 pkt->setLE<uint8_t>(regs.intrctrl());
205 regs.intrctrl.master_int_enable(0);
206 break;
207 case GEN_ATTNSTATUS:
208 assert(size == sizeof(regs.attnStatus));
205 regs.intrctrl.master_int_enable(0);
206 break;
207 case GEN_ATTNSTATUS:
208 assert(size == sizeof(regs.attnStatus));
209 pkt->set(regs.attnStatus);
209 pkt->setLE<uint32_t>(regs.attnStatus);
210 regs.attnStatus = 0;
211 break;
212 default:
213 panic("Read request to unknown register number: %#x\n", daddr);
214 }
215 pkt->makeAtomicResponse();
216 return pioDelay;
217 }

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239}
240
241void
242CopyEngine::CopyEngineChannel::channelRead(Packet *pkt, Addr daddr, int size)
243{
244 switch (daddr) {
245 case CHAN_CONTROL:
246 assert(size == sizeof(uint16_t));
210 regs.attnStatus = 0;
211 break;
212 default:
213 panic("Read request to unknown register number: %#x\n", daddr);
214 }
215 pkt->makeAtomicResponse();
216 return pioDelay;
217 }

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239}
240
241void
242CopyEngine::CopyEngineChannel::channelRead(Packet *pkt, Addr daddr, int size)
243{
244 switch (daddr) {
245 case CHAN_CONTROL:
246 assert(size == sizeof(uint16_t));
247 pkt->set(cr.ctrl());
247 pkt->setLE<uint16_t>(cr.ctrl());
248 cr.ctrl.in_use(1);
249 break;
250 case CHAN_STATUS:
251 assert(size == sizeof(uint64_t));
248 cr.ctrl.in_use(1);
249 break;
250 case CHAN_STATUS:
251 assert(size == sizeof(uint64_t));
252 pkt->set(cr.status() | (busy ? 0 : 1));
252 pkt->setLE<uint64_t>(cr.status() | (busy ? 0 : 1));
253 break;
254 case CHAN_CHAINADDR:
255 assert(size == sizeof(uint64_t) || size == sizeof(uint32_t));
256 if (size == sizeof(uint64_t))
253 break;
254 case CHAN_CHAINADDR:
255 assert(size == sizeof(uint64_t) || size == sizeof(uint32_t));
256 if (size == sizeof(uint64_t))
257 pkt->set(cr.descChainAddr);
257 pkt->setLE<uint64_t>(cr.descChainAddr);
258 else
258 else
259 pkt->set(bits(cr.descChainAddr,0,31));
259 pkt->setLE<uint32_t>(bits(cr.descChainAddr,0,31));
260 break;
261 case CHAN_CHAINADDR_HIGH:
262 assert(size == sizeof(uint32_t));
260 break;
261 case CHAN_CHAINADDR_HIGH:
262 assert(size == sizeof(uint32_t));
263 pkt->set(bits(cr.descChainAddr,32,63));
263 pkt->setLE<uint32_t>(bits(cr.descChainAddr,32,63));
264 break;
265 case CHAN_COMMAND:
266 assert(size == sizeof(uint8_t));
264 break;
265 case CHAN_COMMAND:
266 assert(size == sizeof(uint8_t));
267 pkt->set(cr.command());
267 pkt->setLE<uint32_t>(cr.command());
268 break;
269 case CHAN_CMPLNADDR:
270 assert(size == sizeof(uint64_t) || size == sizeof(uint32_t));
271 if (size == sizeof(uint64_t))
268 break;
269 case CHAN_CMPLNADDR:
270 assert(size == sizeof(uint64_t) || size == sizeof(uint32_t));
271 if (size == sizeof(uint64_t))
272 pkt->set(cr.completionAddr);
272 pkt->setLE<uint64_t>(cr.completionAddr);
273 else
273 else
274 pkt->set(bits(cr.completionAddr,0,31));
274 pkt->setLE<uint32_t>(bits(cr.completionAddr,0,31));
275 break;
276 case CHAN_CMPLNADDR_HIGH:
277 assert(size == sizeof(uint32_t));
275 break;
276 case CHAN_CMPLNADDR_HIGH:
277 assert(size == sizeof(uint32_t));
278 pkt->set(bits(cr.completionAddr,32,63));
278 pkt->setLE<uint32_t>(bits(cr.completionAddr,32,63));
279 break;
280 case CHAN_ERROR:
281 assert(size == sizeof(uint32_t));
279 break;
280 case CHAN_ERROR:
281 assert(size == sizeof(uint32_t));
282 pkt->set(cr.error());
282 pkt->setLE<uint32_t>(cr.error());
283 break;
284 default:
285 panic("Read request to unknown channel register number: (%d)%#x\n",
286 channelId, daddr);
287 }
288}
289
290

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303
304 int size = pkt->getSize();
305
306 ///
307 /// Handle write of register here
308 ///
309
310 if (size == sizeof(uint64_t)) {
283 break;
284 default:
285 panic("Read request to unknown channel register number: (%d)%#x\n",
286 channelId, daddr);
287 }
288}
289
290

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303
304 int size = pkt->getSize();
305
306 ///
307 /// Handle write of register here
308 ///
309
310 if (size == sizeof(uint64_t)) {
311 uint64_t val M5_VAR_USED = pkt->get();
312 DPRINTF(DMACopyEngine, "Wrote device register %#X value %#X\n", daddr, val);
311 uint64_t val M5_VAR_USED = pkt->getLE<uint64_t>();
312 DPRINTF(DMACopyEngine, "Wrote device register %#X value %#X\n",
313 daddr, val);
313 } else if (size == sizeof(uint32_t)) {
314 } else if (size == sizeof(uint32_t)) {
314 uint32_t val M5_VAR_USED = pkt->get();
315 DPRINTF(DMACopyEngine, "Wrote device register %#X value %#X\n", daddr, val);
315 uint32_t val M5_VAR_USED = pkt->getLE<uint32_t>();
316 DPRINTF(DMACopyEngine, "Wrote device register %#X value %#X\n",
317 daddr, val);
316 } else if (size == sizeof(uint16_t)) {
318 } else if (size == sizeof(uint16_t)) {
317 uint16_t val M5_VAR_USED = pkt->get();
318 DPRINTF(DMACopyEngine, "Wrote device register %#X value %#X\n", daddr, val);
319 uint16_t val M5_VAR_USED = pkt->getLE<uint16_t>();
320 DPRINTF(DMACopyEngine, "Wrote device register %#X value %#X\n",
321 daddr, val);
319 } else if (size == sizeof(uint8_t)) {
322 } else if (size == sizeof(uint8_t)) {
320 uint8_t val M5_VAR_USED = pkt->get();
321 DPRINTF(DMACopyEngine, "Wrote device register %#X value %#X\n", daddr, val);
323 uint8_t val M5_VAR_USED = pkt->getLE<uint8_t>();
324 DPRINTF(DMACopyEngine, "Wrote device register %#X value %#X\n",
325 daddr, val);
322 } else {
323 panic("Unknown size for MMIO access: %d\n", size);
324 }
325
326 if (daddr < 0x80) {
327 switch (daddr) {
328 case GEN_CHANCOUNT:
329 case GEN_XFERCAP:
330 case GEN_ATTNSTATUS:
331 DPRINTF(DMACopyEngine, "Warning, ignorning write to register %x\n",
332 daddr);
333 break;
334 case GEN_INTRCTRL:
326 } else {
327 panic("Unknown size for MMIO access: %d\n", size);
328 }
329
330 if (daddr < 0x80) {
331 switch (daddr) {
332 case GEN_CHANCOUNT:
333 case GEN_XFERCAP:
334 case GEN_ATTNSTATUS:
335 DPRINTF(DMACopyEngine, "Warning, ignorning write to register %x\n",
336 daddr);
337 break;
338 case GEN_INTRCTRL:
335 regs.intrctrl.master_int_enable(bits(pkt->get<uint8_t>(),0,1));
339 regs.intrctrl.master_int_enable(bits(pkt->getLE<uint8_t>(), 0, 1));
336 break;
337 default:
338 panic("Read request to unknown register number: %#x\n", daddr);
339 }
340 pkt->makeAtomicResponse();
341 return pioDelay;
342 }
343

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365void
366CopyEngine::CopyEngineChannel::channelWrite(Packet *pkt, Addr daddr, int size)
367{
368 switch (daddr) {
369 case CHAN_CONTROL:
370 assert(size == sizeof(uint16_t));
371 int old_int_disable;
372 old_int_disable = cr.ctrl.interrupt_disable();
340 break;
341 default:
342 panic("Read request to unknown register number: %#x\n", daddr);
343 }
344 pkt->makeAtomicResponse();
345 return pioDelay;
346 }
347

--- 21 unchanged lines hidden (view full) ---

369void
370CopyEngine::CopyEngineChannel::channelWrite(Packet *pkt, Addr daddr, int size)
371{
372 switch (daddr) {
373 case CHAN_CONTROL:
374 assert(size == sizeof(uint16_t));
375 int old_int_disable;
376 old_int_disable = cr.ctrl.interrupt_disable();
373 cr.ctrl(pkt->get());
377 cr.ctrl(pkt->getLE<uint16_t>());
374 if (cr.ctrl.interrupt_disable())
375 cr.ctrl.interrupt_disable(0);
376 else
377 cr.ctrl.interrupt_disable(old_int_disable);
378 break;
379 case CHAN_STATUS:
380 assert(size == sizeof(uint64_t));
381 DPRINTF(DMACopyEngine, "Warning, ignorning write to register %x\n",
382 daddr);
383 break;
384 case CHAN_CHAINADDR:
385 assert(size == sizeof(uint64_t) || size == sizeof(uint32_t));
386 if (size == sizeof(uint64_t))
378 if (cr.ctrl.interrupt_disable())
379 cr.ctrl.interrupt_disable(0);
380 else
381 cr.ctrl.interrupt_disable(old_int_disable);
382 break;
383 case CHAN_STATUS:
384 assert(size == sizeof(uint64_t));
385 DPRINTF(DMACopyEngine, "Warning, ignorning write to register %x\n",
386 daddr);
387 break;
388 case CHAN_CHAINADDR:
389 assert(size == sizeof(uint64_t) || size == sizeof(uint32_t));
390 if (size == sizeof(uint64_t))
387 cr.descChainAddr = pkt->get();
391 cr.descChainAddr = pkt->getLE<uint64_t>();
388 else
392 else
389 cr.descChainAddr = (uint64_t)pkt->get() |
393 cr.descChainAddr = (uint64_t)pkt->getLE<uint32_t>() |
390 (cr.descChainAddr & ~mask(32));
391 DPRINTF(DMACopyEngine, "Chain Address %x\n", cr.descChainAddr);
392 break;
393 case CHAN_CHAINADDR_HIGH:
394 assert(size == sizeof(uint32_t));
394 (cr.descChainAddr & ~mask(32));
395 DPRINTF(DMACopyEngine, "Chain Address %x\n", cr.descChainAddr);
396 break;
397 case CHAN_CHAINADDR_HIGH:
398 assert(size == sizeof(uint32_t));
395 cr.descChainAddr = ((uint64_t)pkt->get<uint32_t>() <<32) |
399 cr.descChainAddr = ((uint64_t)pkt->getLE<uint32_t>() << 32) |
396 (cr.descChainAddr & mask(32));
397 DPRINTF(DMACopyEngine, "Chain Address %x\n", cr.descChainAddr);
398 break;
399 case CHAN_COMMAND:
400 assert(size == sizeof(uint8_t));
400 (cr.descChainAddr & mask(32));
401 DPRINTF(DMACopyEngine, "Chain Address %x\n", cr.descChainAddr);
402 break;
403 case CHAN_COMMAND:
404 assert(size == sizeof(uint8_t));
401 cr.command(pkt->get());
405 cr.command(pkt->getLE<uint8_t>());
402 recvCommand();
403 break;
404 case CHAN_CMPLNADDR:
405 assert(size == sizeof(uint64_t) || size == sizeof(uint32_t));
406 if (size == sizeof(uint64_t))
406 recvCommand();
407 break;
408 case CHAN_CMPLNADDR:
409 assert(size == sizeof(uint64_t) || size == sizeof(uint32_t));
410 if (size == sizeof(uint64_t))
407 cr.completionAddr = pkt->get();
411 cr.completionAddr = pkt->getLE<uint64_t>();
408 else
412 else
409 cr.completionAddr = pkt->get() |
413 cr.completionAddr = pkt->getLE<uint32_t>() |
410 (cr.completionAddr & ~mask(32));
411 break;
412 case CHAN_CMPLNADDR_HIGH:
413 assert(size == sizeof(uint32_t));
414 (cr.completionAddr & ~mask(32));
415 break;
416 case CHAN_CMPLNADDR_HIGH:
417 assert(size == sizeof(uint32_t));
414 cr.completionAddr = ((uint64_t)pkt->get() <<32) |
418 cr.completionAddr = ((uint64_t)pkt->getLE<uint32_t>() <<32) |
415 (cr.completionAddr & mask(32));
416 break;
417 case CHAN_ERROR:
418 assert(size == sizeof(uint32_t));
419 (cr.completionAddr & mask(32));
420 break;
421 case CHAN_ERROR:
422 assert(size == sizeof(uint32_t));
419 cr.error(~pkt->get() & cr.error());
423 cr.error(~pkt->getLE<uint32_t>() & cr.error());
420 break;
421 default:
422 panic("Read request to unknown channel register number: (%d)%#x\n",
423 channelId, daddr);
424 }
425}
426
427void

--- 326 unchanged lines hidden --- 		424 break;
425 default:
426 panic("Read request to unknown channel register number: (%d)%#x\n",
427 channelId, daddr);
428 }
429}
430
431void

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