sinic.cc (11719:e832056deaed) | sinic.cc (12087:0e082672ac6b) |
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1/* 2 * Copyright (c) 2004-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 77 unchanged lines hidden (view full) --- 86{ 87} 88 89Device::Device(const Params *p) 90 : Base(p), rxUnique(0), txUnique(0), 91 virtualRegs(p->virtual_count < 1 ? 1 : p->virtual_count), 92 rxFifo(p->rx_fifo_size), txFifo(p->tx_fifo_size), 93 rxKickTick(0), txKickTick(0), | 1/* 2 * Copyright (c) 2004-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 77 unchanged lines hidden (view full) --- 86{ 87} 88 89Device::Device(const Params *p) 90 : Base(p), rxUnique(0), txUnique(0), 91 virtualRegs(p->virtual_count < 1 ? 1 : p->virtual_count), 92 rxFifo(p->rx_fifo_size), txFifo(p->tx_fifo_size), 93 rxKickTick(0), txKickTick(0), |
94 txEvent(this), rxDmaEvent(this), txDmaEvent(this), | 94 txEvent([this]{ txEventTransmit(); }, name()), 95 rxDmaEvent([this]{ rxDmaDone(); }, name()), 96 txDmaEvent([this]{ txDmaDone(); }, name()), |
95 dmaReadDelay(p->dma_read_delay), dmaReadFactor(p->dma_read_factor), 96 dmaWriteDelay(p->dma_write_delay), dmaWriteFactor(p->dma_write_factor) 97{ 98 interface = new Interface(name() + ".int0", this); 99 reset(); 100 101} 102 --- 427 unchanged lines hidden (view full) --- 530 intrTick = curTick(); 531 } 532 533 DPRINTF(EthernetIntr, "going to schedule an interrupt for intrTick=%d\n", 534 intrTick); 535 536 if (intrEvent) 537 intrEvent->squash(); | 97 dmaReadDelay(p->dma_read_delay), dmaReadFactor(p->dma_read_factor), 98 dmaWriteDelay(p->dma_write_delay), dmaWriteFactor(p->dma_write_factor) 99{ 100 interface = new Interface(name() + ".int0", this); 101 reset(); 102 103} 104 --- 427 unchanged lines hidden (view full) --- 532 intrTick = curTick(); 533 } 534 535 DPRINTF(EthernetIntr, "going to schedule an interrupt for intrTick=%d\n", 536 intrTick); 537 538 if (intrEvent) 539 intrEvent->squash(); |
538 intrEvent = new IntrEvent(this, true); | 540 541 intrEvent = new EventFunctionWrapper([this]{ cpuInterrupt(); }, 542 name(), true); |
539 schedule(intrEvent, intrTick); 540} 541 542void 543Base::cpuInterrupt() 544{ 545 assert(intrTick == curTick()); 546 --- 745 unchanged lines hidden (view full) --- 1292 /* 1293 * Keep track of pending interrupt status. 1294 */ 1295 UNSERIALIZE_SCALAR(intrTick); 1296 UNSERIALIZE_SCALAR(cpuPendingIntr); 1297 Tick intrEventTick; 1298 UNSERIALIZE_SCALAR(intrEventTick); 1299 if (intrEventTick) { | 543 schedule(intrEvent, intrTick); 544} 545 546void 547Base::cpuInterrupt() 548{ 549 assert(intrTick == curTick()); 550 --- 745 unchanged lines hidden (view full) --- 1296 /* 1297 * Keep track of pending interrupt status. 1298 */ 1299 UNSERIALIZE_SCALAR(intrTick); 1300 UNSERIALIZE_SCALAR(cpuPendingIntr); 1301 Tick intrEventTick; 1302 UNSERIALIZE_SCALAR(intrEventTick); 1303 if (intrEventTick) { |
1300 intrEvent = new IntrEvent(this, true); | 1304 intrEvent = new EventFunctionWrapper([this]{ cpuInterrupt(); }, 1305 name(), true); |
1301 schedule(intrEvent, intrEventTick); 1302 } 1303} 1304 1305void 1306Device::serialize(CheckpointOut &cp) const 1307{ 1308 int count; --- 255 unchanged lines hidden --- | 1306 schedule(intrEvent, intrEventTick); 1307 } 1308} 1309 1310void 1311Device::serialize(CheckpointOut &cp) const 1312{ 1313 int count; --- 255 unchanged lines hidden --- |