i8254xGBe.hh (12064:39f4d937dd22) i8254xGBe.hh (12087:0e082672ac6b)
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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93 // Event and function to deal with RDTR timer expiring
94 void rdtrProcess() {
95 rxDescCache.writeback(0);
96 DPRINTF(EthernetIntr,
97 "Posting RXT interrupt because RDTR timer expired\n");
98 postInterrupt(iGbReg::IT_RXT);
99 }
100
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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93 // Event and function to deal with RDTR timer expiring
94 void rdtrProcess() {
95 rxDescCache.writeback(0);
96 DPRINTF(EthernetIntr,
97 "Posting RXT interrupt because RDTR timer expired\n");
98 postInterrupt(iGbReg::IT_RXT);
99 }
100
101 //friend class EventWrapper<IGbE, &IGbE::rdtrProcess>;
102 EventWrapper<IGbE, &IGbE::rdtrProcess> rdtrEvent;
101 EventFunctionWrapper rdtrEvent;
103
104 // Event and function to deal with RADV timer expiring
105 void radvProcess() {
106 rxDescCache.writeback(0);
107 DPRINTF(EthernetIntr,
108 "Posting RXT interrupt because RADV timer expired\n");
109 postInterrupt(iGbReg::IT_RXT);
110 }
111
102
103 // Event and function to deal with RADV timer expiring
104 void radvProcess() {
105 rxDescCache.writeback(0);
106 DPRINTF(EthernetIntr,
107 "Posting RXT interrupt because RADV timer expired\n");
108 postInterrupt(iGbReg::IT_RXT);
109 }
110
112 //friend class EventWrapper<IGbE, &IGbE::radvProcess>;
113 EventWrapper<IGbE, &IGbE::radvProcess> radvEvent;
111 EventFunctionWrapper radvEvent;
114
115 // Event and function to deal with TADV timer expiring
116 void tadvProcess() {
117 txDescCache.writeback(0);
118 DPRINTF(EthernetIntr,
119 "Posting TXDW interrupt because TADV timer expired\n");
120 postInterrupt(iGbReg::IT_TXDW);
121 }
122
112
113 // Event and function to deal with TADV timer expiring
114 void tadvProcess() {
115 txDescCache.writeback(0);
116 DPRINTF(EthernetIntr,
117 "Posting TXDW interrupt because TADV timer expired\n");
118 postInterrupt(iGbReg::IT_TXDW);
119 }
120
123 //friend class EventWrapper<IGbE, &IGbE::tadvProcess>;
124 EventWrapper<IGbE, &IGbE::tadvProcess> tadvEvent;
121 EventFunctionWrapper tadvEvent;
125
126 // Event and function to deal with TIDV timer expiring
127 void tidvProcess() {
128 txDescCache.writeback(0);
129 DPRINTF(EthernetIntr,
130 "Posting TXDW interrupt because TIDV timer expired\n");
131 postInterrupt(iGbReg::IT_TXDW);
132 }
122
123 // Event and function to deal with TIDV timer expiring
124 void tidvProcess() {
125 txDescCache.writeback(0);
126 DPRINTF(EthernetIntr,
127 "Posting TXDW interrupt because TIDV timer expired\n");
128 postInterrupt(iGbReg::IT_TXDW);
129 }
133 //friend class EventWrapper<IGbE, &IGbE::tidvProcess>;
134 EventWrapper<IGbE, &IGbE::tidvProcess> tidvEvent;
130 EventFunctionWrapper tidvEvent;
135
136 // Main event to tick the device
137 void tick();
131
132 // Main event to tick the device
133 void tick();
138 //friend class EventWrapper<IGbE, &IGbE::tick>;
139 EventWrapper<IGbE, &IGbE::tick> tickEvent;
134 EventFunctionWrapper tickEvent;
140
141
142 uint64_t macAddr;
143
144 void rxStateMachine();
145 void txStateMachine();
146 void txWire();
147

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157 */
158 void chkInterrupt();
159
160 /** Send an interrupt to the cpu
161 */
162 void delayIntEvent();
163 void cpuPostInt();
164 // Event to moderate interrupts
135
136
137 uint64_t macAddr;
138
139 void rxStateMachine();
140 void txStateMachine();
141 void txWire();
142

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152 */
153 void chkInterrupt();
154
155 /** Send an interrupt to the cpu
156 */
157 void delayIntEvent();
158 void cpuPostInt();
159 // Event to moderate interrupts
165 EventWrapper<IGbE, &IGbE::delayIntEvent> interEvent;
160 EventFunctionWrapper interEvent;
166
167 /** Clear the interupt line to the cpu
168 */
169 void cpuClearInt();
170
171 Tick intClock() { return SimClock::Int::ns * 1024; }
172
173 /** This function is used to restart the clock so it can handle things like

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279 /** If the address/len/head change when we've got descriptors that are
280 * dirty that is very bad. This function checks that we don't and if we
281 * do panics.
282 */
283 void areaChanged();
284
285 void writeback(Addr aMask);
286 void writeback1();
161
162 /** Clear the interupt line to the cpu
163 */
164 void cpuClearInt();
165
166 Tick intClock() { return SimClock::Int::ns * 1024; }
167
168 /** This function is used to restart the clock so it can handle things like

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274 /** If the address/len/head change when we've got descriptors that are
275 * dirty that is very bad. This function checks that we don't and if we
276 * do panics.
277 */
278 void areaChanged();
279
280 void writeback(Addr aMask);
281 void writeback1();
287 EventWrapper<DescCache, &DescCache::writeback1> wbDelayEvent;
282 EventFunctionWrapper wbDelayEvent;
288
289 /** Fetch a chunk of descriptors into the descriptor cache.
290 * Calls fetchComplete when the memory system returns the data
291 */
292 void fetchDescriptors();
293 void fetchDescriptors1();
283
284 /** Fetch a chunk of descriptors into the descriptor cache.
285 * Calls fetchComplete when the memory system returns the data
286 */
287 void fetchDescriptors();
288 void fetchDescriptors1();
294 EventWrapper<DescCache, &DescCache::fetchDescriptors1> fetchDelayEvent;
289 EventFunctionWrapper fetchDelayEvent;
295
296 /** Called by event when dma to read descriptors is completed
297 */
298 void fetchComplete();
290
291 /** Called by event when dma to read descriptors is completed
292 */
293 void fetchComplete();
299 EventWrapper<DescCache, &DescCache::fetchComplete> fetchEvent;
294 EventFunctionWrapper fetchEvent;
300
301 /** Called by event when dma to writeback descriptors is completed
302 */
303 void wbComplete();
295
296 /** Called by event when dma to writeback descriptors is completed
297 */
298 void wbComplete();
304 EventWrapper<DescCache, &DescCache::wbComplete> wbEvent;
299 EventFunctionWrapper wbEvent;
305
306 /* Return the number of descriptors left in the ring, so the device has
307 * a way to figure out if it needs to interrupt.
308 */
309 unsigned
310 descLeft() const
311 {
312 unsigned left = unusedCache.size();

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379 */
380 void pktComplete();
381
382 /** Check if the dma on the packet has completed and RX state machine
383 * can continue
384 */
385 bool packetDone();
386
300
301 /* Return the number of descriptors left in the ring, so the device has
302 * a way to figure out if it needs to interrupt.
303 */
304 unsigned
305 descLeft() const
306 {
307 unsigned left = unusedCache.size();

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374 */
375 void pktComplete();
376
377 /** Check if the dma on the packet has completed and RX state machine
378 * can continue
379 */
380 bool packetDone();
381
387 EventWrapper<RxDescCache, &RxDescCache::pktComplete> pktEvent;
382 EventFunctionWrapper pktEvent;
388
389 // Event to handle issuing header and data write at the same time
390 // and only callking pktComplete() when both are completed
391 void pktSplitDone();
383
384 // Event to handle issuing header and data write at the same time
385 // and only callking pktComplete() when both are completed
386 void pktSplitDone();
392 EventWrapper<RxDescCache, &RxDescCache::pktSplitDone> pktHdrEvent;
393 EventWrapper<RxDescCache, &RxDescCache::pktSplitDone> pktDataEvent;
387 EventFunctionWrapper pktHdrEvent;
388 EventFunctionWrapper pktDataEvent;
394
395 bool hasOutstandingEvents() override;
396
397 void serialize(CheckpointOut &cp) const override;
398 void unserialize(CheckpointIn &cp) override;
399 };
400 friend class RxDescCache;
401

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479 * @return packet can't be sent out because it's a multi-descriptor
480 * packet
481 */
482 bool packetMultiDesc() { return pktMultiDesc;}
483
484 /** Called by event when dma to write packet is completed
485 */
486 void pktComplete();
389
390 bool hasOutstandingEvents() override;
391
392 void serialize(CheckpointOut &cp) const override;
393 void unserialize(CheckpointIn &cp) override;
394 };
395 friend class RxDescCache;
396

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474 * @return packet can't be sent out because it's a multi-descriptor
475 * packet
476 */
477 bool packetMultiDesc() { return pktMultiDesc;}
478
479 /** Called by event when dma to write packet is completed
480 */
481 void pktComplete();
487 EventWrapper<TxDescCache, &TxDescCache::pktComplete> pktEvent;
482 EventFunctionWrapper pktEvent;
488
489 void headerComplete();
483
484 void headerComplete();
490 EventWrapper<TxDescCache, &TxDescCache::headerComplete> headerEvent;
485 EventFunctionWrapper headerEvent;
491
492
493 void completionWriteback(Addr a, bool enabled) {
494 DPRINTF(EthernetDesc,
495 "Completion writeback Addr: %#x enabled: %d\n",
496 a, enabled);
497 completionAddress = a;
498 completionEnabled = enabled;
499 }
500
501 bool hasOutstandingEvents() override;
502
503 void nullCallback() {
504 DPRINTF(EthernetDesc, "Completion writeback complete\n");
505 }
486
487
488 void completionWriteback(Addr a, bool enabled) {
489 DPRINTF(EthernetDesc,
490 "Completion writeback Addr: %#x enabled: %d\n",
491 a, enabled);
492 completionAddress = a;
493 completionEnabled = enabled;
494 }
495
496 bool hasOutstandingEvents() override;
497
498 void nullCallback() {
499 DPRINTF(EthernetDesc, "Completion writeback complete\n");
500 }
506 EventWrapper<TxDescCache, &TxDescCache::nullCallback> nullEvent;
501 EventFunctionWrapper nullEvent;
507
508 void serialize(CheckpointOut &cp) const override;
509 void unserialize(CheckpointIn &cp) override;
510 };
511
512 friend class TxDescCache;
513
514 TxDescCache txDescCache;

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503 void serialize(CheckpointOut &cp) const override;
504 void unserialize(CheckpointIn &cp) override;
505 };
506
507 friend class TxDescCache;
508
509 TxDescCache txDescCache;

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